以雙載子接面電晶體為基礎之矽仿視網膜分析與設計及其在影像邊緣萃取和運動物體偵測的應用

Abstract

本論文的主旨在於闡述以雙載子接面電晶體為基礎之矽仿視網膜的分析與 設計及其在影像邊緣萃取和運動物體偵測的應用。論文中包含下列四個主 要部分：(1) 以雙載子接面電晶體為基礎之矽仿視網膜的影像平整函數的 特性描述及分析；(2) 具有影像平整化可調整的新型以雙載子接面電晶體 為基礎之矽仿視網膜的設計製作；(3) 結合以雙載子接面電晶體為基礎之 矽仿視網膜及暫態式零點跨越感測器的新型運動偵測器的設計製作；(4) 結合以雙載子接面電晶體為基礎之矽仿視網膜及臨界感測器的新型影像邊 緣萃取器的設計製作。首先，本論文中針對以雙載子接面電晶體為基礎之 矽仿視網膜的平整函數在考慮共基極雙載子接面電晶體陣列的基極電阻偏 壓效應下發展出單點及多點輸入的分析式模型。透過此模型，矽仿視網膜 中雙載子接面電晶體平整網路的影像平整化的動作原理可以清楚地被瞭解 。並且，影響影像平整函數的參數及設計規範也可由此模型獲得。由所推 導出的公式中可看出以雙載子接面電晶體為基礎之矽仿視網膜隨著影像的 對比及背景不同，會有適應式的影像平整化能力。為了驗證此模型的正確 性，我們以0.6um互補式金氧半技術設計及製作了實驗晶片。量測及模擬 結果皆指出此模型的正確性，並證實此矽仿視網膜的性能優點。因此，此 分析式模型可以有效率地模擬無法以SPICE模擬的大尺寸矽仿視網膜的特 性。其次，本論文中提出並分析一具有簡單緊密結構的改良型以雙載子接 面電晶體為基礎之矽仿視網膜。在此新結構中，用來模仿視網膜中水平單 元(horizontal cells)的雙載子接面電晶體平整網路是以加強型N通道金 氧半場效電晶體置於互補式金氧半技術的寄生雙載子接面電晶體的基極間 而構成的。在此，N通道金氧半場效電晶體可工作於次臨界區或強反轉區 ，以提供大範圍的通道電阻值，因此，網路平整化的特性可以大範圍的調 整。我們以0.5um互補式金氧半技術設計及製作了具有64*64像素的實驗晶 片，並透過量測驗證其平整區域的可調性及其可用來偵測運動物體的動態 特性。此改良結構很適合於做超大型積體化及結合於互補式金氧半智慧型 感測器中。再者，根據由生物模型所啟發的影像邊緣臨界感測演算法，本 論文中提出並製作一結合以雙載子接面電晶體為基礎之矽仿視網膜及臨界 感測器的新型影像邊緣萃取器。此萃取器的每一像素都含有一個矽仿視網 膜單元，及其所屬的邊緣感測器，且影像的攫取及邊緣影像的產生皆是以 平行化進行。此外，不須增加介面電路下，每一像素內還可加入DRAM儲存 單元，以儲存所萃取出的邊緣影像做為後續處理系統的輸入資料。我們 以0.25um DRAM技術設計了具有128*128像素的實驗晶片，其每一像素的面 積為30*30mm^2，並透過模擬驗證其正確的動作。此顆實驗晶片的功率消 耗在3.3V下約為150mW。最後，本論文中提出並製作一結合以雙載子接面 電晶體為基礎之矽仿視網膜及暫態式零點跨越感測器的新型運動偵測器。 此偵測器採用一修正型token-based delay-and-correlate運算演算法來 偵測特定的運動速度及方向，此外，為了達成速度及方向的高度選擇性， 關連訊號是採用二元化脈波訊號。此偵測器的基本偵測單元的電路架構非 常緊密，含有一個矽仿視網膜單元、一個暫態式零點跨越感測器、二個延 遲路徑、及四個關連器。我們以0.6um互補式金氧半技術設計及製作了具 有32*32基本偵測單元的實驗晶片，每個基本偵測單元的面積為100*100 um^2。而此新型運動偵測器的功能都一一經由量測驗證，根據量測結果顯 示，此實驗晶片的偵測速度範圍可達56mm/sec~5m/sec，偵測方向範圍為0 degree ~ 360 degree，功率消耗在5V下小於20mW。經由模擬及實驗證實 ，本論文中所發展出的電路架構對於設計模擬人類的視覺系統的單一晶片 系統具有極大的用處。未來將朝這個領域繼續研究。 In this thesis the BJT-based silicon retinas and their applications onimage edge extraction and moving object detection are designed and analyzed.The main parts of this thesis include: (1) the characterization and analysis ofimage smoothing functions in the BJT-based silicon retina; (2) theimplementation of the new BJT-based silicon retina using tunable imagesmoothing capability; (3) the implementation of the new image edge extractor using BJT-based silicon retina and thresholding detector; (4) the design of thenew motion sensor with BJT-based silicon retina and temporal zero-crossing detector.Firstly, the analytical models of the smoothing function of the BJT-based silicon retina under both single-point and multiple-point stimuli havebeen developed by considering the base resistance bias effect of the common-base BJT array. Through the analytical models, the operatingprinciple of the image smoothing performed by the BJT smoothing network of the BJT-based silicon retina can be well understood. Moreover, theparameters which affect the image smoothing characteristics of the BJT- basedsilicon retina can be characterized by the developed models and suitabledesign guidelines can be obtained. It may be seen from the derived equations that the smoothing characteristics depend upon the image contrast andbackground, which makes the BJT-based silicon retina adaptive in imagesmoothing. Experimental chip has been designed and fabricated by 0.6 um CMOS technology. Both measurement results and SPICE simulation results have substantiated the developed analytical model and verified the performance advantages of the BJT-based silicon retina. Thus the model can be used to efficiently simulate large-size BJT-based silicon retina which cannot be simulated in SPICE.Secondly, an improved BJT-based silicon retina with simple and compact structure is proposed and analyzed. In the proposed structure, the BJT smoothing network which models the layer of horizontal cells in the vertebrate retina is implemented by placing enhancement n-channel MOSFETs among the bases of parasitic BJTs existing in CMOS process toform an unique and compact structure. The nMOSFET can be operated in subthreshold region or strong-inversion region to provide a wide-range tunable channel resistance controlled by the common gate bias. Thus the smoothing characteristics can be tuned in a wide range. Moreover, an extra emitter isincorporated with each BJT at the pixel to act as the row switch. This reducesthe cell area of the silicon retina and increases the resolution. Using the proposed new structure, an experimental 64*64 BJT-based silicon retina chip has been fabricated by using 0.5um CMOS technology. The measurement results on the tunability of the smooth area in the smoothing network as well asthe dynamic characteristics of the proposed silicon retina in detecting moving objects have been presented. It is believed that theimproved structure is verysuitable for the VLSI implementation of the retina and its application systemsCMOS smart sensors.Thirdly, a compact and real-time 2-D edge sensor integrated with the embedded DRAM is proposed and analyzed. In the proposed edge sensor, the computation algorithm is based upon the algorithm inspired by the biologicalmodel of detecting spatial edges by thresholding the outputs of the siliconretina. Each basic detection cell in the sensor has a compact architecture which consists of one BJT- based silicon retina cell, one thresholding edge detector, and a DRAM storage cell. The significant features of the edge sensor are that the image acquisition and edge image generation can be performed in a parallel manner, and the DRAM storage cell can be incorporated into eachcell without additional interface circuits to store the resultant edge image forfurther processing by following processing system, such as neural network.Using the proposed architecture, an experimental 128*128 edge sensor chipwith a cell size of 30*30 um2 has been designed by using 0.25 um DRAM technology. The correct operations of the designed sensor chip have been verified through simulations. The complete sensor consumes about 150 mW at 3.3V.Finally, a 2-D velocity- and direction-selective visual motion sensorwith BJT- based silicon retina and temporal zero-crossing detector is proposed and implemented. In the proposed sensor, the modified token-based delay-and-correlate computational algorithm is adopted to detect the specified speed and direction of moving object images. Moreover, binary pulsed signals areused as correlative signals to increase the velocity and direction selectivities. Each basic detection cell in the sensor has a compact architecture which consists of one BJT-based silicon retina cell, one current-input edge extractor, two delay paths, and four correlators.Using the proposed architecture, an experimental 32*32 visual motion sensor chip with a cell size of 100*100 mm2 has been designed and fabricatedby using 0.6 mm CMOS technology. The correct operations of the fabricatedsensor chip have been verified through measurements. The measured rangesof selectively detected on-chip velocity and direction in the fabricated sensor chip are 56mm/sec~5m/sec (1120pixel/sec~105 pixel/sec) and 0 degree ~360 degree, respectively. The complete sensor consumes 20mW at 5V.From the above results, it is believed that the proposed BJT-basedsilicon retina and its application architectures on edge extraction and motiondetection have a great potential in system-on-a-chip design of machine visionsystems which mimic human vision to achieve various efficient imageprocessing. Further researches in this field will be conducted in the future.