標題: 以CPLD為基礎泛用型交流馬達控制IC之研製
Design and Implementation of a CPLD-Based Universal AC Motor Control IC
作者: 江晉毅
Chiang, Chin-Yi
鄒應嶼
Ying-Yu Tzou
電控工程研究所
關鍵字: 馬達控制IC;可規劃邏輯;伺服控制;解耦控制;電流控制;motor control IC;programmable logic;servo control;decoupling control;current control
公開日期: 1997
摘要: 本論文以複雜型可規劃邏輯晶片(complex programmable logic device, CPLD)實現可應用於交流同步馬達與感應馬達伺服控制的泛用型控制IC, 此控制IC採用轉子磁場導向向量控制架構,包含電流迴路控制器、解耦控 制器與伺服控制器,為一功能完整的交流馬達控制IC。在現有的交流伺服 驅動相關研究中,是架構最完整的交流馬達控制IC。所研製的控制IC具有 可程式化的特點,經由相關控制暫存器的設定,即可完成交流伺服馬達的 控制。控制IC之電流迴路以十位元實現,採用相位領先/落後控制器,控 制架構可選用靜止座標或同步旋轉座標實現,也可加入反電動勢補償,取 樣頻率設定範圍為78 Hz至50 kHz。解耦控制與伺服控制則以十六位元實 現,解耦控制器可經由模式選擇及相關控制暫存器設定,完成交流馬達不 同光編碼器解析度及馬達極數的解耦控制,感應馬達方面,亦可經由解耦 控制暫存器完成扭矩控制。伺服控制包含速度迴路控制與位置迴路控制, 位置迴路採用具有前饋路徑的比例積分控制架構,速度迴路則採用二階數 位濾波器,伺服控制之命令型態可選擇脈衝或數值命令,取樣週期為電流 迴路的整數倍,設定範圍為0.3 Hz至50 kHz。此控制IC實現約使用九萬個 閘數量(gate count)的CPLD資源,在控制IC設計驗證方面,本文除進行硬 體 電路模擬之外,也以不同的伺服實驗驗證此控制IC的特性,實驗結果 顯示所研製的控制IC具有相當好的控制性能,且設計的功能皆可正確運作 。 This thesis presents the design and implementation of a universal ac motor control IC using complex programmable logic device (CPLD). The proposed control IC is constructed under rotor flux oriented control, and may be used for vector control of both permanent magnet and induction ac motors. There are three major units in this control IC: voltage/current vector controller, decoupling controller, and servo controller. The control IC is programmable, and control parameters can be set by an external microprocesos. In the realization of the current vector controller, 10-bit integer arithmetic is adopted, and the current vector control can be either operating in stationary or synchronous reference frame. The sampling rate can be programmed from 78 Hz to 50 kHz. In decoupling and servo controllers, 16-bit integer arithmetic is adopted to realize the control algorithm. Decoupling controller is used for the decoupling control of both permanent magnet and induction ac motors. Servo controller accomplishes speed and poition loop control. Proportional and integral with feedforward control is adopted in position loop and a second-order digital filter is used in speed loop. About 90% of 100 thousands typical gates CPLD is used to realize the proposed control IC. In this thesis, software simulation and servo experiments have been carried out to verify the control IC functions. Experimental results show that the control IC has very excellent characteristics and all of the designed functions can work correctly.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT860591037
http://hdl.handle.net/11536/63215
Appears in Collections:Thesis