降低不匹配效應之二階Σ-Δ類比至數位轉換器

Abstract

本論文提出一個有效架構來降低二階MASH (multistage noise shaping) 類比數位轉換器之不匹配效應。因製程偏差所造成之電容不匹配效應會造成類比數位轉換器之訊噪比下降，此新架構利用資料流的交互轉換，有效補償電容不匹配效應所造成之影響。透過國家晶片系統設計中心委託台灣積體電路製造股份有限公司以0.35微米互補式金氧半導體的製程製造。整個類比數位轉換器已經被完整地設計、製造與量測完成。 為了比較新架構比起傳統架構更能有效抑制電容不匹配效應所造成之影響，同時將兩種架構放進晶片中，並刻意製造20% 之電容不匹配。量測結果顯示，新架構之訊噪比幾乎不受電容不匹配所影響。傳統架構的佈局面積是600x1500 μm2；新架構的佈局面積是700x1500 μm2。在3v的操作電壓，22.05kHz 的輸入訊號，取樣頻率為5.6448MHz下，量測到之訊噪比為68.8dB；1kHz 的輸入訊號，取樣頻率為256kHz下，量測到之訊噪比為90.6dB

A compensation technique for reducing mismatch errors of CMOS second-order MASH (multistage noise shaping) delta-sigma analog to digital converter (ADC) is proposed in this thesis. The signal-to-noise ratio (SNR) of ADC will reduce due to the mismatch of capacitors by process variation. An innovative compensation method which re-locate data path by switched capacitor is realized in a 0.35-mm CMOS technology supported by Taiwan Semiconductor Manufacturing Company via Chip Implementation Center. The proposed ADC is completely designed, fabricated and tested. Both conventional and new proposed architectures are on the chip, and 20% capacitor mismatch is placed on purpose. Measured results exhibit that the new proposed MASH has better immunity to capacitor mismatch errors effect than conventional MASH. The chip area of conventional MASH is 600x1500μm2; the new proposed MASH is 700x1500μm2. Measured SNR is 68.8dB with 22.05 kHz input signal and 5.6448MHz sampling rate; 90.6dB with 1 kHz input signal and 256 kHz sampling rate in 3v supply voltage.