完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Kim, Keunwoo | en_US |
dc.contributor.author | Kuang, Jente B. | en_US |
dc.contributor.author | Gebara, Fadi H. | en_US |
dc.contributor.author | Ngo, Hung C. | en_US |
dc.contributor.author | Chuang, Ching-Te | en_US |
dc.contributor.author | Nowka, Kevin J. | en_US |
dc.date.accessioned | 2014-12-08T15:08:11Z | - |
dc.date.available | 2014-12-08T15:08:11Z | - |
dc.date.issued | 2009-12-01 | en_US |
dc.identifier.issn | 0018-9383 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TED.2009.2030657 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/6383 | - |
dc.description.abstract | This paper presents a new SRAM cell using a global back-gate bias scheme in dual buried-oxide (BOX) FD/SOI CMOS technologies. The scheme uses a single global back-gate bias for all cells in the entire columns or subarray, thereby reducing the area penalty. The scheme improves 6T SRAM standby leakage, read stability, write ability, and read/write performance. The basic concept of the proposed scheme is discussed based on physical analysis/equation to facilitate device parameter optimization for SRAM cell design in back-gated FD/SOI technologies. Numerical 2-D mixed-mode device/circuit simulation results validate the merits and advantages of the proposed scheme. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | FD/SOI device | en_US |
dc.subject | mix-mode simulator | en_US |
dc.subject | read stability | en_US |
dc.subject | substrate bias | en_US |
dc.title | TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TED.2009.2030657 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
dc.citation.volume | 56 | en_US |
dc.citation.issue | 12 | en_US |
dc.citation.spage | 3033 | en_US |
dc.citation.epage | 3040 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000271951700020 | - |
dc.citation.woscount | 1 | - |
顯示於類別: | 期刊論文 |