化學氣相沉積介電薄膜特性對CMP技術與記憶體元件應用之影響研究

Abstract

本研究以工業應用整合角度出發，系統性的研究ULSI後段製程中常用介電薄膜製程與其材料特性，以此為基礎研究結合介電膜特性與CMP技術之整合製程，以提昇ULSI淺溝渠絕緣製程表現，同時發展出介電膜與化學機械拋光整合定則之學理依據，並經由材料與ULSI記憶元件特性分析瞭解獲得較佳元件特性之材料與製程需求。 本論文首先研究CVD氧化矽及氮化矽介電材料特性，使用PECVD法所成長之富矽氧化矽底層可提供均一之表面，提高SACVD法成長之氧化矽膜厚均一性與填隙能力。提高富矽氧化矽中之矽含量將提昇膜中Si-H鍵結及矽微晶之含量，導致高膜表面粗糙度及非晶矽未鍵結鍵(*Si*Si3)濃度，且高矽原子濃度將提昇電子偏極化、抑制區域結構之完整性，因而改變其鍵結、引發薄膜應力、化學活性、膜折射率等特性之改變。此外提昇氮化矽沉積反應中SiH4/NH3流量比將提高拉伸應力以及氫原子去吸附力，導致高蝕刻率及拋光速率，同時降低膜中氮原子含量與薄膜密度，此乃因較高的Si-H鍵結提高膜孔隙度，引發高拉伸應力，以至於提高水解及離子之擴散速率因而提高薄膜的蝕刻率與研磨速率。 進一步改變薄膜的沉積反應可以製備高研磨速率比的介電層，整合這些多層薄膜於ULSI之淺溝渠絕緣製程中，可以提高化學機械拋光之效率與終止層之表現，因而有助於全表面平坦化、無碟陷現象之淺溝渠絕緣層。深入研究介電層與CMP製程之交互作用，歸納出包含介電層與CMP製程不均勻度、介電層厚度、製程平坦化效率、元件幾何數據、拋光速率與誤差度之整合定則，可以有效的用於製程整合中以評估研磨時間與介電層厚度，更有經濟效益的提昇平坦化製程。 整合這些多層薄膜於ULSI記憶元件製程中，發現這些薄膜將影響元件特性，O3/TEOS 所成長之氧化矽較SOG對4-T SRAM元件特性有更佳之改善，水氣與氫離子由後段製程中釋放將劣化記憶元件特性，使用富矽氧化矽於ILD、IMD及護層中可以改善SRAM、NVM之元件特性與可靠度，膜中所含非晶矽未鍵結鍵(*Si*Si3)可以有效吸附後段製程中所產生之氫、水汽等移動性離子降低對元件所造成之影響，確保記憶元件中資料儲存之可靠度；因此，降低氮化矽中氫含量亦可進一步改善元件特性與可靠度。

From an industrial application perspective, this study systematically investigated the material characteristics of typically used ULSI back-end-of-line dielectrics and their CMP performance. The rule of INTEGRATE proposed in this study provides the optimization scheme for ULSI CVD and CMP processes with cost effectivity and promising process performance. Besides, based on results of material analysis and ULSI memory device performance, the optimal process integration scheme could be identified for the implementation of proper dielectric materials with specific characteristics into the memory devices. This also yielded better and more reliable memory device performances. In this study, the dielectric material characteristics of CVD oxide and nitride films were systematically developed and investigated. PECVD silicon rich oxide (SRO) provided an identical substrate surface for the subsequent O3/TEOS SACVD process, leading to elimination of the substrate sensitivity and hence good thickness uniformity and gap fill capability. As the Si content increased in the SRO, the extra Si atoms would be incorporated in form of Si-H bonds which eventually led to the formation of Si nanocrystals. The extra Si-H bonds inserted inside the oxide network inhibited the perfect growth of oxide locally, leading to elongated bonds and hence a tensile stress component and enhanced chemical activity in the oxide. They also enhanced electron polarizability, resulting in higher RI, higher density of a-Si-like dangling bond (*Si*Si3) and the presence of more silicon nanocrystals. Increasing the SiH4/NH3 flow ratio during PECVD nitride reactions resulted in the decreases in RI, Si:N atomic ratio, amount of hydrogen desorption, wet etch rate and CMP removal rate (R/R) as well as the increases in compressive stress, thin film density and N-H bonding density. The existence of more Si-H bonds increased the porosity of PECVD SiNx, leading to the increases in both chemical etch rate and CMP removal rate due to the lower diffusion coefficient of water or H+ in the nitrides. Advanced process integration based on the fundamental of CMP removal rate selectivity between dielectric materials was developed. By using multi-layered thin film structure (SiO2/SiNx/SiO2) with modifications in their characteristics to adjust the CMP remove rate selectivity and efficiency of polish stopper, a one-step CMP process for ULSI shallow trench isolation (STI) process was developed. Globally-planarized surface and dishing-free wide trench areas could be achieved based on this study. An integrated solution to the IMD/CMP process which included the Integral Nonuniformity, Thickness of dielectric, Efficiency of planarization, Geometry of device, Removal rate, And its variation for CMP Time Estimation (INTERGATE) was also proposed to estimate the required dielectric thickness and optimal polishing time in order to enhance the throughput and reliability of the IMD-CMP process. The implementation of the fine-tuned CVD dielectrics into ULSI memory devices exposed some potential impacts of dielectric material characteristics upon memory device performance. The incorporation of O3-TEOS oxides was shown to yield better 4-T SRAM device performance than conventional SOG process. Water diffusion from oxide and hydrogen released from nitride were both responsible for MOS device and memory device characteristics degradation. Incorporation of a PECVD-SRO underlayer improved the device characteristics and reliability of the 4-T SRAM and non-volatile memory (NVM) devices. The a-Si-like dangling bonds (*Si*Si3) in IMD films served as effective trapping centers for hydrogen or moisture and hence protected device from the attack by backend process-induced mobile charges. Thus the resistance of 4-T SRAM poly-Si load resistors and NVM floating gate device integrity were maintained at high and stable quality with minimum deviation, and improved device performance and data storage reliability could be achieved. Further improvement in memory device characteristics could be fulfilled by optimizing the characteristics of PECVD SiO2/SiNx passivation layers. PECVD nitride with the highest amount hydrogen desorption showed the most significant impact on MOS device characteristics, as well as highest NVM floating gate drift and 4-T SRAM deterioration rate.