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dc.contributor.author呂台欣en_US
dc.contributor.authorTai-Hsin Luen_US
dc.contributor.author張明峰en_US
dc.contributor.authorMing-Feng Changen_US
dc.date.accessioned2014-12-12T02:20:17Z-
dc.date.available2014-12-12T02:20:17Z-
dc.date.issued1998en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT870392032en_US
dc.identifier.urihttp://hdl.handle.net/11536/64053-
dc.description.abstract在本篇論文中,我們提出了一個理論架構,能夠同時解決在網格狀的環境中做腳位配置(pin assignment),以及詳細繞線(detail routing)的問題。腳位配置所使用的方法是找出每個模組及訊號線的重心,再根據這些重心決定每個腳位的位置。詳細繞線則是使用線段搜尋理論(line search algorithm),這個理論能夠快速的找到可行的路徑。因為我們針對腳位配置以及詳細繞線的問題同時處理,所以我們能夠在腳位配置階段就考慮到繞線區域的擁塞程度,進而改善最終繞線的結果。這個理論有實際處理一顆高效能微處理機的繞線問題。實驗結果顯示我們的理論能夠有效地減少處理違反時間延遲上限的訊號線時所需要使用到的緩衝器數目,並且能夠增加處理的訊號線數目。zh_TW
dc.description.abstractIn this paper, we propose a GSR (Global Signal Routing) algorithm. This algorithm focuses on grid routing problem. It is capable of dealing simultaneously with both pin assignment and detail routing. The pin assignment method uses a center-of-mass algorithm to minimize the wire length. The detail routing algorithm uses line search algorithm, which is very fast in finding a valid path. The integration of pin assignment and detail routing gives good results because we can consider the routing area usage during both pin assignment stage and detail routing stage. The algorithm is applied on the design of a high performance microprocessor. Experiment results show that our algorithm indeed considerably reduces the number of wires violating timing delay constraints, and increase the number of routable wires.en_US
dc.language.isozh_TWen_US
dc.subject腳位配置zh_TW
dc.subject詳細繞線zh_TW
dc.subject時間延遲zh_TW
dc.subjectpin assignmenten_US
dc.subjectdetail routingen_US
dc.subjecttime delayen_US
dc.title高效能微處理機之第四、五金屬層全域訊號繞線zh_TW
dc.titleGlobal Signal Routing for A High Performance Microprocessor Using Metal 4 and 5 Layersen_US
dc.typeThesisen_US
dc.contributor.department資訊科學與工程研究所zh_TW
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