高效能微處理機之全域訊號繞線與加入緩衝器

Abstract

要提升微處理機的效能最有效的方法就是提高它的工作時脈，但是要提高時脈，首先就要克服微處理機內部訊號傳遞的時間延遲問題。另一方面，在微處理機有限的繞線空間下如何有效的提高繞線能力(routability)也是需要克服的問題。 本篇論文的設計目標是國科會前瞻性微處理機設計與製造計畫，這項計畫的目的在於發展x86相容的高性能微處理機。為了因應這顆微處理機的架構我們設計了特殊的繞線架構來處理這顆微處理器的繞線問題。在這個繞線環境中，我們將全域訊號(Global signals)以繞經製程的第四，五層金屬來處理，以利用這兩層金屬較低的電阻和電容特性來減少時間延遲。但是全域訊號必須避開在第四，五層製程中原有的時脈與電源的網格狀分布，因此全域訊號只能利用剩餘的空間來進行繞線。 我們以去年發展的繞線程式(router)為基礎，提出一個包含繞線與加入緩衝器的方法，這個方法具備較強的繞線能力並且能夠有效減少訊號線的時間延遲問題。在繞線能力方面，我們利用pin re-assignment and reroute方法和兩種不同的繞線模式來提高繞線能力；在減少時間延遲方面，我們利用dynamic programming based buffer insertion method來加入緩衝器以減少內部訊號線的時間延遲問題。在利用Buffer insertion method的同時，我們也考慮了微處理機地板規劃所能允許加入緩衝器的位置。實驗的結果顯示我們的方法能夠處理完所有的全域訊號線的繞線問題，同時大幅度的減少訊號線的時間延遲問題。

Electronic systems now perform a wide variety of tasks in our daily life. The growing sophistication of applications continually pushed the design of integrated circuits and electronic systems to higher and higher performance. It has been an effective way to improve the performance by increasing the working frequency. Nevertheless, it is difficult to meet the timing budget on the signal transmission delay and complete all signal connections in the limited routing space when increasing the working frequency. This thesis focuses on the global signal routing problem for a high performance microprocessor, and a router is implemented for our design target, NSC98 microprocessor. In NSC98 microprocessor, the critical nets of the top-level inter-module interconnections are routed passing through the metal-4 and metal-5 layers. The metal-4 and metal-5 layers have technology characteristics of lower resistance and capacitance, so that the global signal delay can be reduced. The routing space for global signals is the remainder space of the grid structures used by clock and power/ground distributions. Thus, Lu has developed global signal router on regular grid-structural channels to handle the special design [12]. This thesis extents Lu’s work and develops a global signal routing and buffer insertion algorithm for our router. The new router completes all global signal connections, including wires that were not connected in Lu’s router. Our algorithm uses pin re-assignment and reroute techniques to improve the routability, and a dynamic programming based buffer insertion is applied to minimize the interconnect delay. The experiment results show that our algorithm can complete all global signals routing and meet the timing requirements with much fewer number of buffers.