高性能微處理機之地板規劃與繞線

Abstract

隨著積體電路製程技術的進步，晶片內的電晶體個數及工作頻率快速的增加，電路的複雜性越來越高，電路的設計需由一個龐大的團隊來共同研發完成。一般來說，現行的晶片設計採用階層式的設計，將整個晶片切割成數個區塊來進行，當設計完成後再進行整合的工作。而設計流程通常是採用「瀑布式」模式，即當一個階段完成後，將此結果送到下個階段當輸入。如此的模式若沒有考慮到其對後段流程的影響，當後段設計碰到問題時，只好回到前面階段重新設計，如此將耗費許多時間在重複執行此流程。在本篇論文中，我們針對NSC98這顆高性能微處理機的頂層實體佈局提出一設計流程，此流程包括了地板規劃(floorplanning)、腳位配置(pin assignment)以及繞線(routing)三個步驟。由於NSC98有特殊的設計，並且晶片的面積非常地大，而無法使用Cadence的Preview/Silicon Ensemble來進行自動化佈局，所以我們針對我們的需求，自行發展程式來進行整個流程。我們在初步地板規劃完成後，進行地板規劃的評估，避免在腳位配置或繞線時，碰到錯誤而得重新地板規劃。最後我們完成了NSC98的頂層實體佈局，並且得到不錯的結果。

The rapid advance in VLSI technology results in an exponential increase in chip transistor counts and a significant increase in clock frequency. In general, large system design usually uses a hierarchical design approach, where the chip is divided into blocks. The blocks are developed separately and integrated after they are completed. A typical design flow can be depicted as a waterfall model, where a design stage is completed and the results are passed on to the next stage. The design of each stage can affect the quality of later stage designs. If there are problems unsolved in later stages, system redesign may be required for the early stages. In this thesis, we develop a design flow for the top level physical layout design of NSC98, including floorplanning, pin assignment and routing. In floorplanning design, we consider the factors that affect the performance of pin assignment and routing. In addition to using Cadence tools for floorplanning, we have developed pin assignment and routing CAD tools to complete our design. Finally we designed the top level physical layout of a high performance microprocessor NSC98 using the design flow.