雙模式處理機的Java至ARM轉碼器

Abstract

Java/ARM雙模式處理機可以直接用硬體的方式來執行bytecodes和ARM指令。所以，Java/ARM雙模式處理機具有了用硬體來加速Java程式執行的優點，又兼備了和ARM軟體相容的能力。而為了達到Java/ARM雙模式處理的目的，我們在ARM處理機中加入了一Java至ARM的硬體轉碼器。此轉碼器在處理機的架構上是介於指令擷取單元和解碼器之間。當雙模式處理機處於Java執行模式時，轉碼器會先將bytecodes轉換成對映的ARM指令後，再行解碼、運算的動作。在本篇論文中，首先規畫了Java執行模式下的暫存器使用方式，稱為堆疊至暫存器的對映，以作為設計轉碼器的依據。接下來，在配合Java/ARM雙模式處理機是簡單管線架構和降低硬體複雜度的考量下，設計了一對一轉碼器，其從轉碼功能上來看，有著一個時脈週期只能轉換出一個ARM指令的限制。最後，以提昇Java程式執行的效能為出發點，提出了一對多轉碼器結合指令折疊技術的理論模型，並以軌跡驅動模擬的方法來評估該模型所帶來的效能增益。由實驗結果顯示，使用一對二轉碼器的設計方式，加上指令折疊的機制，可以比使用一對一轉碼器的設計方式提升百分之十五的整體效能。

Java/ARM dual mode processors are capable of executing both bytecodes and ARM instructions in hardware directly. The advantages of this processor are offering a better speed to run Java and being compatible with ARM. In order to achieve the goal of dual mode processing, we design a Java-to-ARM hardware code translator. This translator is placed in between fetcher and decoder. When Java/ARM dual mode processor is Java executing mode, the translator converts bytecodes into ARM instructions sequentially. In the fisrt part of this thesis, we propose a stack to register mapping approach, which specifies the usage of register file in Java executing mode. Then, according to the nature of Java/ARM processor’s pipelining architecture and to decrease hardware complexity, we design a one-to-one translator, which could only translate out one ARM instruction per clock cycle. In the last part of this thesis, we purpose a one-to-many translator with instruction folding methodology to fold the ARM instructions that had been translated out but not decoded yet to improve the overall performance. According to the trace-driven simulation result, if the translator is capable of translating out two ARM instructions per cycle with instruction folding mechanism, the performance may be up to 15%.