自動驗證程式產生器及涵蓋範圍分析器的整合

Abstract

現今超大型積體電路的設計及製造技術演進十分快速，電路的設計驗證工作隨著超大型積體電路設計愈趨複雜也愈趨困難，如超純量微處理機的設計驗證。傳統的隨機驗證程式產生器有一些缺點，例如低涵蓋範圍以及會產生無窮迴圈等。因此，設計高涵蓋範圍的自動驗證程式產生器是很需要的。在這篇論文中，我們發展一套自動驗證程式產生器。它利用涵蓋範圍分析器所分析的涵蓋範圍資料，來引導下一個驗證程式的產生，以提高整體的涵蓋範圍。此種機制稱為回饋機制。為避免產生無窮迴圈，我們提出資源鎖定方法，它的基本觀念是避免某些資源被其他可能產生無窮迴圈的指令所修改。實驗結果不僅顯示我們產生的驗證程式不會有無窮迴圈的問題，採用的回饋機制也確實能夠提高自動驗證程式產生器的涵蓋範圍。與現有的一個方法比較，我們的整合方法使涵蓋範圍提高了60%。

VLSI design and manufacturing technologies progress very fast nowadays. Verification becomes harder as VLSI designs, such as a superscalar microprocessor design, tend to be more complex. Traditional randomly test program generators have some problems, such as low coverage and having infinite loops, etc. Thus, designing an ATPG (Automatic Test Program Generator) with high coverage is desired. In this thesis, we use a feedback mechanism, that utilizes the coverage information from the coverage tool in the ATPG's next generation process to raise verification coverage. To prevent generating infinite loops in test programs, a resource locking scheme is proposed. The resource locking scheme is used to lock those resources from being modified by other generated instructions that may result in generating infinite loops. Experimental results not only show that test programs generated have no infinite loop, but also demonstrate that the feedback mechanism indeed enhance the ATPG generation process to produce test programs with high coverage. Our integrated tool raises the coverage up to 60% in comparison with an existing approach.