場射電晶體之模型與深次微米超大型積體電路之靜態電流測試

Abstract

本論文包含兩個子題，第一個子題是場射電晶體-其模型與驅動電路，第二個子題是超大型積體電路靜態電流測試-新方法與其電流感測器。 一、場射電晶體-其模型與驅動電路 在場效發射電晶體模型方面，已開發了兩種既簡單準確又能坎入電路模擬軟體的模型。第一種模型是建立在法洛挪漢(Fowler-Nordheim)之電流密度與電場之關係上，但考慮了空間電荷效應及陰極尖端表面之類似指數型式的電荷分佈，模型的參數萃取程序也包含在論文中。第二種模型也是建立在法洛挪漢之電流密度對電場關係上，計算圓形陰極尖端表面上的電流密度分佈時，引用了一個電場式子。對整個表面之電流密度做積分得到陰極電流，而做相同的積分但只對部分面積做積分得到閘極電流。此模型的參數萃取程序包含在論文中。兩種模型和參數萃取程序已經應用在實驗元件上而有很好的準確度。 當場效發射陣列應用在顯示器須一個掃瞄驅動器。由於場效發射陣列之大電容(典型值為5個微微法拉) ，驅動電路通常很慢。本論文使用電壓控制電流源設計成快速驅動電路，克服了上述問題，而且此電路具有齊一電流驅動、灰階控制及低功率之優點。 二、超大型積體電路靜態電流測試-新方法與其電流感測器 對於超大型積體電路靜態電流測試方面，本論文首先對2006~2012年之深次微米領域作靜態電流分佈之預估，此預估考慮了製程變動及不同輸入向量。其中製程變動是超大型積體電路之靜態電流變動的最主要因素。靜態電流的期望值幾乎和電路大小成線性關係，然而標準誤差粗略地正比於電路大小的平方根，根據估計結果，本論文提出四種靜態電流測試方法，這四種方法乃是比較兩個不同的輸入向量下或兩個副電路之靜態電流。 論文中也提出一種能應用於自動量測儀及內建電流感測器之快速感測方法，動態電流快速地被一個低電阻開關旁路掉，靜態電流未穩定前即被感測。根據上述所提出之靜態電流測試法及感測方法，本論文提出三種低電壓輸入、低供給電壓及高解析度之外接及內建電流感測器，這些感測器能夠比較待測電路在不同的輸入向量下或不同待測電路之靜態電流，取代傳統上之絕對值的量測，它們有電路分割數目少、低電壓輸入、高解析度及低供給電壓之優點，改善了障礙偵測及診斷能力，使得這些感測器能夠應用在深次微米領域數位超大型積體電路靜態電流測試上。 除了上述三種感測器，本論文亦提出三種低電壓輸入、低供給電壓、高解析度及快速內建電流感測器，這些感測器能夠量測靜態電流之絕對值。

This dissertation contains two topics. The first topic is the field emission transistor-its model and driving circuits. The second one is the VLSI IDDQ testing-new schemes and related current sensors, either built-in or off-chip. I. Field Emission Transistor-Its Model and Driving Circuits For the modeling of field emission triode, two simple but accurate models, which can be incorporated into circuit simulation programs such as SPICE, for the field emission triode are developed. The first model is based on the Fowler-Nordheim current density-electrical field relationship but takes into account the space charge effect and the exponential-like charge distribution on the surface of the tip of the device. A procedure is developed to extract the parameters of the model. The second model is also based on the Fowler-Nordheim current density-electrical field relationship. An electric field form is adopted to calculate the current density distribution along the surface of the sphere-shape tip. The cathode current is obtained by integration of the current density over the emission surface. The gate current is derived by the same integration but over part of the emission area. A procedure to extract the values for the parameters of the model is also given. Both of the models and the procedures have been applied to experimental devices to demonstrate their accuracy. The field emission array (FEA), when used as a display device, requires a scanning driving circuit. Due to the large FEA capacitance (typically 5pF for one pixel), the driving circuit is usually slow. In this thesis, a new driving circuit, which employs the voltage controlled current source (VCCS), overcomes the above-mentioned problem, thus can reach a high driving speed. In addition, the circuit has the advantages of a uniform current driving, the gray level control and the low power consumption. II. VLSI IDDQ Testing-New Schemes and Related Current Sensors For the IDDQ testing, the distribution of defect-free IDDQ of a CMOS deep submicron VLSI circuit for the years of 2006~2012 is estimated. The estimation considers the process variation, which dominates the IDDQ variation in VLSI circuit, and different input vectors. The expected value is almost linearly proportional to the size of the circuit. However, the standard deviation is roughly proportional to the square root of the circuit size. Based on the estimation, four new IDDQ testing schemes, which compare the IDDQ currents between two input vectors or two partitioned sub-circuits (CUTs), are proposed. A fast sensing scheme, which can be applied to the Automatic Testing Equipment (ATE) and the built-in current sensor (BICS), is proposed. The transient current is rapidly bypassed by a very low resistance of a switch. The quiescent current is sampled before it reaches to a stable value. Based on the proposed IDDQ testing schemes and the sensing scheme, three types of off-chip and built-in current sensors, which are low input voltage, low power supply and high resolution, are proposed. The sensors, instead to detect the absolute value of the IDDQ currents of the CUT, compare the IDDQ currents of the CUT under different input test vectors or between the IDDQ currents of two CUTs. They have the advantages of reduction in the circuit partitioning number, low input voltage, high resolution, low power supply voltage, and improved fault detectability and diagnosability, making them very suitable to be applied to testing deep submicron digital ULSI CMOS ICs. In addition to the above three types of sensors, three types of low input voltage, low power supply, highly sensitive and fast BICSs, which can measure the absolute value of the IDDQ current, are also proposed and demonstrated.