記憶體靜態電流測試

Abstract

記憶體靜態電流測試 研究生：李坤地 指導教授：李崇仁 教授 國立交通大學 電子工程學系 電子研究所碩士班 摘要 本論文主要是研究記憶體在正常及有缺陷時的靜態電流特性，並提出新的記憶體靜態電流測試方法。在一般的內建式電流測試方法中，最嚴重的問題便是造成效能的降低及於深次微米範疇時，次漏電流太大將使得此方法變得不實際。於本論文中，我們研究記憶體於有缺陷存在時，在記憶體各部份電路的電流上所表現的障礙效應。由觀察結果，我們提出一個新的靜態電流測試架構，一方面使其對記憶體的效能影響降至最低，並可完全避免於深次微米範疇時之次漏電流太大之問題。 我們提出的靜態電流測試架構是將電流感測器置於記憶體的寫入電路中。由模擬結果，發現此種方式可測出所有的的短路障礙，及靜態隨機存取記憶體之部分斷路障礙。且可診斷其中的大部分。

IDDQ Testing on Memories Student: Kun-Ti Lee Adviser: Prof. Chung Len Lee Department of Electronics Engineering & Institute of Electronics National Chiao Tung University Abstract In this thesis, we investigate the quiescent current characteristics of fault-free and faulty memories and propose a novel IDDQ testing method. In the general IDDQ testing, a serious problem is the performance degradation due to adding of the extra-current sensing circuit. Also, in the deep submicron regime, the increased subthreshold current will make this technique impractical. In this thesis, we first study the quiescent currents drawn for each part of the under-test memory both for fault-free and faulty circuit. Form the simulation results, we proposed a new IDDQ testing architecture to test the circuit. The architecture minimizes the performance degradation problem and avoids the deep submicron subthreshold problem. The architecture we propose is to connect current sensor to the write-circuit of the memory such that the performance degradation is reduced to minimum and the subthreshold problem will never occur. The simulation result, show that the scheme can detect all the short faults and some of open faults for SRAM. It can also diagnose most of the faults. Chinese Abstract ....................................... i English Abstract .......................................ii Acknowlegment.......................................... iv Contents ............................................... v Table Captions ....................................... vii Figure Captions ..................................... viii Chapter 1 Introduction 1.1 Conventional voltage based testing on memories...... 1 1.2 IDDQ testing on memories ........................... 2 1.3 Outline of Thesis....................................4 Chapter 2 IDDQ Simulation on DRAM and SRAM 2.1 RAM Structure....................................... 6 2.2 DRAM ............................................... 7 2.21 DRAM simulation model ...........................9 2.22 DRAM Fault Model .............................. 11 2.23 Simulation results ............................ 13 2.24 Diagnosis ..................................... 19 2.3 SRAM .............................................. 21 2.31 SRAM simulation model.......................... 23 2.32 SRAM Fault Model .............................. 24 2.33 Simulation results and diagnosis .............. 26 2.4 Summary............................................ 31 Chapter 3 A New BICS Scheme for Memory IDDQ Testing 3.1 Typical BICS Testing Scheme ................ 33 3.2 New BICS Testing Scheme............................ 34 3.3 Built-In Current Sensor (BICS) .................... 34 3.4 New BICS Scheme for DRAMs.......................... 39 3.5 New BICS Scheme for SRAMs.......................... 42 3.5.1 Bridging defects ............................. 42 3.5.2 Open defects ................................. 44 3.6 Area Overhead and Test Length Estimation........... 52 3.7 Summary ............................................53 Chapter 4 Conclusion ………………………………………… 54 References …………………………………………………… 55