基於漏電流統計分析程序與異常值偵測技術之穩態電流測試流程

Abstract

本論文提出了一個基於機率統計估算穩態電流測試閥值的方法。 基於本論文提及的觀測結果，我們開發了能夠快速且有效地適應多種 晶片電流值分布之演算法。並且，展示了一個基於統計模擬的分析架 構，以用於估算以標準單元為基礎設計之電路的漏電流機率分布。此 架構需求之輸入檔案皆為現代電路設計流程常見且支援的檔案格式。 我們展示了有效且精確的漏電流預測結果，並討論了此結果與真實量 測數據間的差異情形。

This thesis introduces a statistical approach to estimate valid IDDQ test threshold. We developed a quick and efficient algorithm which can fit various type of chip current distributions based on our observations presented in this thesis. Also, a simulation based statistical analysis framework is exhibited to estimate leakage current distribution of standard cell based designs. The required input files of this framework are in commonly used format in modern industrial design flow. Our final result demonstrated effective and accurate prediction of leakage current variation. The gap between our estimation and real silicon result is also discussed.