P型複晶矽閘極結構之硼穿透效應之研究

Abstract

在此論文中，我們提出二種新的技術來抑制P型複晶矽閘極結構之硼穿透效應及改善其閘極氧化層之完整性。首先，我們採用一種將氟化硼(BF2+)離子佈植到雙層矽化鈷(CoSi)/非晶矽，用以製作優異之複晶矽鈷金屬矽化物閘極元件之新製程。此製程是利用矽化鈷作為離子佈植障礙層，來降低硼擴散和離子佈植所造成的缺陷，進而得到較小的平帶電壓變動和較好的崩潰電場及崩潰電荷量特性。此外，在低溫下形成自行校準金屬矽化物的同時，下層仍保有非晶矽的狀態，能更進一步地阻擋硼擴散和改善閘極氧化層之特性。因此，結合非晶矽和鈷矽化物佈植障礙層，可以有效地阻擋硼擴散。 然而，在鈷閘極金屬矽化物下之閘極氧化層品質是重要的，但卻鮮被研究﹔因此，我們採用將氟化硼離子佈植到雙層矽化鈷/非晶矽並作爐管退火處理之製程，以矽化鈷厚度和佈植能量為參數，來探討閘極氧化層之可靠度。當矽化鈷厚度和退火溫度增加時，會導致閘極氧化層特性及平帶電壓變動惡化；此外，雖然較薄的矽化鈷有較好的閘極氧化層特性，但其高溫熱穩定性卻會變差。再者，較淺的離子佈植深度和較低的退火溫度，雖能減低硼擴散，但亦會引發複晶矽閘極空乏區之效應；因以，在維持閘極介電層可靠度的同時，需對矽化鈷厚度、離子佈植能量和退火溫度等參數作適當的選取，方能使元件達到最佳化。 為了順應未來短時間熱處理製程的趨勢，我們選擇以快速退火取代爐管退火，研究將氟化硼佈植到雙層矽化鈷/非晶矽，以矽化鈷厚度和佈植能量為參數，來探討矽化鈷對閘極氧化層之影響。在高溫熱穩定性方面，較薄之矽化鈷經快速退火處理，比經爐管退火之表現要好；此外，矽化鈷經快速退火處理，因其有較低的熱能供給，是故比爐管退火處理者，有較小之平帶電壓變動及優異的閘極氧化層特性。 最後，另一種抑制硼穿透的方法是利用電感耦合電漿，對堆疊型複晶矽閘極介面作氮化處理；而此氮化處理，在後續離子佈植退火後，不僅僅在閘極氮化處理介面，而且在閘極氧化層，均會產生一層富含氮雜質，能更有效地阻擋硼的擴散。再者，此氮化處理位置愈接近閘極氧化層，退火後，在閘極氧化層中氮含量就愈高，更能抑制硼穿透效應及改善閘極氧化層之可靠度。然而，直接在閘極氧化層作氮化處理，平帶電壓雖較未做氮化處理的控制組小，但因氮電漿直接對閘極氧化層造成嚴重損害，導致崩潰電場及崩潰電荷量變差。

In this thesis, two new techniques are proposed to suppress the boron penetration and improve the gate oxide integrity in the p+ poly-Si gate structure. Firstly, a novel process that implants BF2+ ions into thin bilayered CoSi/amorphous-Si (a-Si) films has been introduced to form excellent cobalt silicided p+ poly-Si gates. The process utilizes the cobalt silicide layer as an implantation barrier to minimize the boron diffusion by reducing the projection range and implant-induced defects, thus resulting in smaller flat-band voltage (Vfb) shift and better characteristics of the breakdown field (Ebd) and charge to breakdown (Qbd). Moreover, the a-Si underlayer is simultaneously kept during the formation of the low-temperature self-aligned silicide (SAD) process to further block the boron diffusion and improve gate oxide integrity. Hence, the effects of not only using the CoSi layer as an implantation barrier but also keeping the a-Si underlayer during the initial silicide formation both significantly suppress the boron penetration through thin gate oxide into underlying Si substrates. As a result, this scheme shows good feasibility for further deep-submicron dual gate CMOS technology. However, the dielectric strength of thin gate oxide beneath cobalt polycide gate electrodes is an important issue, which has not been extensively investigated. Consequently, the reliability of thin gate oxides fabricated by implanting BF2+ ions into bilayered CoSi/a-Si films and subsequent furnace annealing has been studied as a function of cobalt silicide thickness and implantation energy. Significant degradation of gate oxide integrity and flat-band voltage shifts were found with increasing cobalt silicide thickness and annealing temperature. It is shown that although thinner cobalt silicide can result in excellent integrity of gate dielectric, it also leads to worse thermal stability at high annealing temperature. Moreover, shallower implantation depth and lower annealing temperature can reduce the boron penetration, but depletion effects in polycrystalline silicon gates are caused accordingly. Hence, appropriate process conditions, involving trade-off among CoSi2 thickness, implantation energy and annealing temperature, must be used to optimize the device performance while retaining the thin dielectric reliability. As for the trend of using low thermal-budget process in the future advanced CMOS technology, the cobalt polycide gate formed by implanting BF2+ ions into the bilayered CoSi/a-Si films and subsequent rapid thermal anneal, instead of long-term furnace annealing, has been studied. The resulting gate oxide integrity is characterized with respect to various silicide thickness and implantation energies. The samples with thinner silicide by RTA treatments possess better high-temperature stability that those by FA treatments. In addition, small flat-band voltage shifts and excellent gate oxide integrity are found for the samples by RTA, as compared to those by FA, attributable to low thermal budget and thus suppression of boron penetration. Finally, the other technique to suppress the boron penetration is nitridizing the stacked poly-Si gates by using Inductively Coupled N2 Plasma (ICNP) system to improve the gate oxide integrity. The ICNP treatments at the interfaces of stacked poly-Si films would create the nitrogen-rich layers not only at the treated poly-Si interface but also in the gate oxide after post implant anneal, thus resulting in effective retardation of boron diffusion. Furthermore, the position of ICNP treatment closer to gate oxides leads to higher nitrogen peaks in the gate oxide region, resulting in further suppression of boron penetration and significant improvement of gate oxide reliability. However, although the samples by the ICNP treatment directly on the gate oxide possess much smaller flat-band voltage (Vfb) shifts than the samples without ICNP treatments, severe degradation of the breakdown field (Ebd) and charge to breakdown (Qbd) values was found and attributed to the severe ICP N2 plasma damage directly on the gate oxide.