高介電材料氧化鋁於元件介電層之應用

Abstract

在深次微米時代,當元件愈做愈小,氧化層越來越薄時,漏電流增大的問題急需解決,而此時高介電材料的應用與取代傳統氧化矽便愈發重要. 我們在這裡利用非常簡單的製程來得到氧化鋁,並以它為介電材料而獲得了介電常數K~ 8到9.8 之間.比起現今最被廣泛研究的氮化矽的介電常數要高.此外,我們利用乾氧直接熱氧化鋁薄膜形成氧化鋁以得到較好的電性. 我們所得到的漏電流在4.8nm氧化鋁厚度時約比2.1nm氧化矽小七個數量級.氧化鋁與矽晶片介面也表現出低介面陷阱密度和與氧化矽電晶體約相同的電子等效遷移率.而可靠性分析方面,我們利用定電流及定電壓所做的測試,均證實氧化鋁的可靠度較佳.

The scaling limit for gate oxide in VLSI is determined by the direct tunneling leakage current. Further device performance improvement can be obtained using a higher dielectric constant material. We have studied the aluminum oxide (Al2O3) as an alternative gate dielectric. In this thesis we report a very simple process to fabricate aluminum oxide (Al2O3) gate dielectric with K (~8 to 9.8) greater than the K of Si3N4. Aluminum oxide (Al2O3) is formed by directed oxidation from thermally evaporated Al. The 4.8nm aluminum oxide (Al2O3) has ~7 orders lower leakage current than equivalent 2.1nm SiO2. Good aluminum oxide (Al2O3)/ Si interface was evidenced by the low interface density of 5*1011 /cm2-ev and compatiable electron effective mobility with thermal SiO2. Good reliability is measured from the small SILC after constant current and constant voltage stress.