互補式金氧半管線化高速類比至數位轉換器之設計與分析

Abstract

摘 要 本文先對管線化ADC的架構加以描述，對於數位修正電路詳加解釋，接著將管線化ADC所可能造成誤差的原因加以探討，並提出解決方法。 本文並描述一個3.3V電壓源，10位元，20M/sample管線化的類比至數位轉換器，這個架構是fully differential作為輸入，輸入的範圍是-1~+1V。主要的元件有:餘數放大器（residue amplifier），比較器 （comparator），D-fliplop 和加法器。架構分為9 級，每級可以得到2bit，其中並包含有數位修正電路，故實際每級僅得到1bit，最後一級得到2bit，最後經過管線與加法器得10bit解析度。餘數放大器還有減法的部份是以開關加電容配合放大器來實現。本文對於此架構的原理與設計方法加以討論與解說，對於Switch-Capacitor circuit layout 也有概略的介紹。 本架構在TSMC，0.6um SPTM CMOS的製程下，以hspice做模擬，模擬的結果符合10bit 解析度，20M 取樣頻率，所需要消耗的功率小於80mW，最後並作layout，送CIC製作晶片。

Abstract In this thesis, the advantage and the architecture of the pipeline ADC is described. The digital error correction technique is explained in detail. Furthermore, the error source of the pipeline analog-to-digital converter is shown and discussed. And there are some solutions to these problems in this thesis. We also illustrate a 10bit resolution, 20MHz sampling rate pipeline ADC. The input of this architecture is a fully differential format, the input range is -1v~+1v. The component in the ADC is the residue amplifier, the comparator, the D-flipflop and the adder. The ADC has 9 stages, each stage get 2 bits and one of them is used for digital error correction. The last stage can get 2 bit. The residue amplifier is implemented by the switch capacitor circuit. The theorem of the circuit and design method is shown and discussed. The layout of the Switch-Capacitor circuit is illustrated also. The ADC was designed using TSMC 0.6um 1P3M CMOS process by chip implement center. The simulation is done by Hspice. The spec of the ADC is 10bit resolution, 20MHz sampling rate, less than 80mW power consumption.