電漿處理後溫差液相沈積含氟矽氧化膜特性之研究及其在銅製程上之應用

Abstract

在本研究中, 首先我們設計並組裝了一部嶄新的自動化液相沈積(LPD)設備。本裝置整體的管路可用PLC控制,避免了人員污染及安全問題。此外,由初步的測試結果發現,利用本裝置所成長的液相沈積氧化矽薄膜具有較佳的特性。 而為了進一步提高溫差液相沈積含氟矽氧化膜(TD-LPD FSG)之可靠性,我們對溫差液相沈積含氟矽氧化膜施以N2O及NH3 電漿處理並研究其抗濕性。結果發現,經N2O電漿處理後之溫差液相沈積含氟矽氧化膜介電常數值雖然略微上昇,但其抗濕性卻有效地被改善。然而, 溫差液相沈積含氟矽氧化膜經NH3電漿處理後則無此效果,僅介電常數值上昇而已。顯然,N2O 電漿處理後之溫差液相沈積含氟矽氧化膜非常適合單一地或與其他介電層結合作為導線間介電層(IMD)。而再根據二次離子質譜(SIMS)及熱脫附質譜儀(TDS) 之分析結果,我們亦提出了一項新的機制來解釋此電漿處理之效應。 接著,我們並首次提出以NH3電漿處理後之溫差液相沈積含氟矽氧化膜來作為銅之阻障介電層。因為具有絕佳之步階覆蓋性､且能有效地阻擋銅擴散,及特優的電性絕緣能力,若使用此阻障介電層來取代高電阻值之阻障金屬層(barrier metal)及襯墊氧化層(oxide liner),將可有效降低銅導線整體電阻及導線間漏電流，可大幅改善電阻-電容延遲(RC delay),因此在未來銅導線/低介電常數(low-K)介電質之嵌刻(damascene)製程中,極具應用潛力。

A novel automatic LPD (liquid phase deposition) bench is designed and assembled. The person-related contamination induced during operation and the security problems of the nowaday equipment is improved. The higher quality of LPD oxides prepared by this novel automatic LPD bench is verified. To further improve the reliability of TD-LPD (temperature-difference liquid phase deposition) FSG, effects of N2O and NH3 plasma annealing on TD-LPD FSG in terms of moisture resistance have been investigated. N2O plasma annealing is effective in improving moisture resistance of the FSG at the expense of increased K value. However, NH3 plasma annealing increases the K value without improving the moisture resistance. Obviously, N2O plasma annealed TD-LPD FSG is promising as IMD, stand-alone or in combination with other dielectric. Accompanied with the investigation of the secondary ion mass spectroscopy (SIMS) and thermal desorption spectroscopy (TDS), a novel mechanism that accounts for plasma annealing effects is proposed. In this work, a novel barrier dielectric prepared by temperature-difference based liquid phase deposition with NH3 plasma annealing is also proposed for the first time. In terms of (1) superior step coverage (95%) (2) effective prevention of Cu penetration and (3) gate oxide level quality, the barrier dielectric is very potential to replace both the barrier metal and the dielectric liner used in Cu/low-K dielectric damascene integration scheme for minimizing RC delay and leakage cu