完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 陳政忠 | en_US |
dc.contributor.author | Cheng-Chung Chen | en_US |
dc.contributor.author | 葉清發 | en_US |
dc.contributor.author | Chin-Fa yeh | en_US |
dc.date.accessioned | 2014-12-12T02:20:45Z | - |
dc.date.available | 2014-12-12T02:20:45Z | - |
dc.date.issued | 1998 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#NT870428032 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/64315 | - |
dc.description.abstract | 利用複晶矽薄膜電晶體製作畫素元件及週邊驅動電路並將之積體化於大面積玻璃基座已是未來製作平面液晶顯示器的趨勢,而複晶矽薄膜電晶體(TFTs)的低溫製程技術將會是一個重要的關鍵。在本論文中,我們利用兩種低溫製程技術來改善複晶矽薄膜電晶體的元件特性,包括金屬再結晶法(MILC)製備高品質主動層技術以及運用通道缺陷的填補技術改善MILC TFTs的元件特性。 在第一個部份中,我們研究金屬致再結晶的關鍵技術並將它運用在複晶矽薄膜電晶體製程。從X光繞射儀(XRD)的譜線裡及拉曼位移譜線中我們驗證了再結晶膜的形成。此外,我們萃取了各種非晶矽薄膜的再結晶速率,希望能建立一個可讓往後製作薄膜電晶體時的參考資料庫。和傳統的600oC固態結晶(SPC)技術比較起來,MILC TFTs 展現了極佳的元件特性。同時,我們也提出了一個新穎的技術,也就是利用雙閘極結構來防止側向結晶的結合邊界(Merging boundary)形成在元件通道中。這個技術大大改善了元件臨界電壓值(Threshold voltage)。另外,這個技術同時也能大幅降低汲極附近橫向電場而有效抑制了元件的漏電流而具有雙重優點。 在第二部分中,我們利用氘氣(deuterium)電漿以及氫氣電漿處理,作為金屬致再結晶複晶矽薄膜電晶體的缺陷填補技術。我們可以發現氫化處理以及氘氣處理均可有效改善元件特性,且改善幅度接近相同。這個結果可以歸因於矽與氘氣以及氫氣鍵結間的同位素效應(isotope effect)。 | zh_TW |
dc.description.abstract | Utilizing polycrystalline silicon thin-film transistors (poly-Si TFTs) as on-glass pixel switching elements and peripheral driver circuits is the future trend for fabricating active-matrix liquid-crystal displays (AMLCDs). Low-temperature processes (LTP) for poly-Si TFTs are important issues. In this thesis, we utilized two low-temperature technologies to improve poly-Si TFTs' performance, including metal induced recrystallization of α-Si and channel defect passivation. In the first part, low-temperature (<550 oC) metal induced crystallization is investigated and applied to TFT's process. X-ray diffraction shows the prefer orientation of <1 1 1> for our MILC films and Raman microscopy reflects the poly-band after crystallization. Furthermore, crystallization rate for different films are also investigated and developed as a database for TFT's process. The MILC TFT's performs excellent characteristics as compare to conventional SPC method. A novel method is utilized to prevent merging boundary from locating in channel by dual gate structure thus improve the device performance. Besides, the leakage current is also sufficiently reduced by the same structure for the lowering of longitudinal electrical field near drain region. In the second part, we utilized deuterium (D2) plasma and hydrogen (H2) plasma treatment to passivate defect densities. Both treatments improved device performance, but no clear difference can be distinguished for H2-and D2- plasma treated samples. This result can be attributed to the isotope effect between Si-H and Si-D bonds. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 複晶矽 | zh_TW |
dc.subject | 薄膜電晶體 | zh_TW |
dc.subject | 複晶矽薄膜電晶體 | zh_TW |
dc.subject | 再結晶 | zh_TW |
dc.subject | 金屬致再結晶 | zh_TW |
dc.subject | 鎳 | zh_TW |
dc.subject | Thin Film Transistor | en_US |
dc.subject | TFT | en_US |
dc.subject | Poly-Silicon | en_US |
dc.subject | recrystallization | en_US |
dc.subject | MILC | en_US |
dc.subject | Nickel | en_US |
dc.subject | metal induced lateral crystallization | en_US |
dc.title | 金屬致再結晶低溫複晶矽薄膜電晶體之研製 | zh_TW |
dc.title | Fabrication of Low Temperature Processed TFT's with Metal Induced Crystallization Method | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
顯示於類別: | 畢業論文 |