薄氧化層n型與p 型金氧半元件中熱載子效應對汲極電流的退化

Abstract

熱載子在深次微米互補式金氧半場效電晶體（CMOS）所起的可靠度問題已經引起廣泛的研究。隨著元件的小型化，觀察元件大小與熱載子效應之間的關係是相當重要的課題，例如閘極氧化層的厚度，通道的長度與寬度，還有隔離的技術等。這可以當作未來元件小型化的一項指標。在這篇論文中，討論了在n型與p型元件中汲極漏電流的增加,和p型元件中導通電流的退化等三個主題。 首先探討在薄氧化層的n型金氧半元件中，熱載子加壓引起汲極漏電流的機制與特性。包括介面缺陷與氧化層電荷的效應。討論在當閘極至源極電壓（Vgs）為零伏時的各種漏電流機制，如汲極到源極端的次臨界電流，能帶至能帶的穿透電流，還有介面缺陷導致的漏電流。我們的結果顯示當工作電壓下降時藉由介面缺面引起之漏電流變成汲極漏電流的主要機制。而且加壓後汲極漏電流的增加跟閘極氧化層的厚度關係密切;對超薄閘極氧化層(30Å)的n型金氧半元件而言，汲極漏電流的增加大部分是由於介面缺陷的產生。然而在較厚氧化層(53Å)的元件中，汲極漏電流顯出兩階段的退化，剛開始由於介面缺陷的產生，漏電流隨時間成指數關係的增加，接著氧化層電荷的生成加快了其增加的速度。 其次，研究淺溝隔絕(STI)和區域性氧化絕緣(LOCOS)的p型金氧半元件在不同通道長度與通道寬度中其熱載子對次臨界漏電流的影響。負的氧化層電荷明顯的增加短通道（≤0.25um）p型金氧半元件的次臨界漏電流。而且在淺溝絕緣邊緣有較強的電子捕捉效率，造成加壓後的淺溝絕緣元件在次臨界區域的部分突出(subthreshold hump)和汲極漏電流嚴重的增加，而在區域性氧化的元件中的元件中並無發現此現象。這個效應當通道越短時越明顯，但是汲極漏電離的增加量跟通道寬度無關。熱載子效應引起的次臨界區域突出變成一個p型金氧半元件微小化的限制因素。 最後，p型金氧半元件中發現了三種導通電流的退化機制，包括氧化層負電荷，介面缺陷，和氧化層正電荷。氧化層負電荷的產生增加導通電流而介面缺陷和氧化層正電荷降低倒通電流。由於在淺溝絕緣邊緣增強衰退效應使得汲極導通電流的退化跟通道寬度有相當的關係。最嚴重的導通電流退化發生在閘極高電壓的加壓，其嚴重的減少汲極電流。介面缺陷跟氧化層正電荷將變成p型金氧半元件導通電流的嚴重問題。

Hot carrier induced reliability issues have received considerable interest in deep-submicron CMOSFET's. As device dimension scales down, it's necessary to investigate the geometric dependencies of hot carrier effects, such as gate oxide thickness, gate length, gate width, and isolation technique. In this thesis, three hot carrier reliability issues, drain leakage current degradation in n-MOSFET's and in p-MOSFET's and on-state current degradation in p-MOSFET's, are discussed. First, the mechanisms and characteristics of hot carrier stress induced drain leakage current degradation in thin-oxide n-MOSFET's are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero Vgs such as drain-to-source subthreshold leakage, band-to-band tunneling current and interface trap induced leakage are taken into account. Our result shows that the trap assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, strong oxide thickness dependence of drain leakage degradation is observed; In ultra-thin gate oxide (30Å) n-MOSFET's, drain leakage current degradation is attributed mostly to interface trap creation while in thicker oxide (53Å) devices the drain leakage current exhibits two-stage degradation, a power law degradation in the initial stage due to interface trap generation followed by an accelerated degradation rate in the second stage caused by oxide charge creation. Next, hot carrier effects in p-MOSFET's with various gate lengths and gate widths are investigated. The subthreshold leakage degradation by using STI and LOCOS isolation techniques are compared. It is found that negative oxide charge can enhance subthreshold leakage significantly in short gate length (£ 0.25mm) p-MOSFET's. Moreover, higher electron trapping efficiency at the edge of STI may cause a subthreshold hump and results in a drastic increase of drain leakage current at zero gate bias. This hump effect is not observed in p-MOSFET's with LOCOS isolation. As gate length is further reduced, this hump effect becomes more serious and may impose a limiting factor on the scaling of a p-MOSFET. Finally, on-state drain current degradation in p-MOSFET's due to negative oxide charge, interface trap, and positive oxide charge creation is studied. Negative oxide charge creation can increase on-state drain current while interface trap and positive oxide charge generation causes a reduction of the current. The most serious degradation occurs at a high Vgs bias stress, which decreases the drain current severely.