矽化鎳之製備及NiSi/p+n接面二極體的之研究

Abstract

本論文主要探討矽化鎳(NiSi)的材料特性與應用於超大型積體電路的相關的製程技術。特性優異的矽化鎳可在400到600 oC之製程溫度範圍內形成在單晶矽基底上。對於在接面深度為0.3微米的p+n接面上形成NiSi而言,最佳的製程是將鍍有鎳金屬的Ni/p+n在爐管中進行500 oC的熱處理30分鐘,如此所得之NiSi/p+n接面二極體的反向偏壓漏電流密度為12.7 nA/cm2。結構為 Ni/(doped)poly-Si/SiO2/Si的試片在爐管中作500 oC 的熱處理30分鐘或在快速退火爐中作450 oC熱處理1分鐘,都可得到電性極佳的NiSi-polycide MOS結構。本論文也探討以離子植入矽化鎳的技術來製作NiSi/p+n淺接面二極體。在BF2+離子以60 KeV能量及1×1015 cm-2劑量植入NiSi/n-Si,並在爐管中作700 oC 的退火處理30分鐘所得之NiSi/p+n接面二極體,其接面深度不及0.15微米,且其反向偏壓漏電流密度僅為20 nA/cm2。

This thesis studies the material properties and process technologies of nickel silicide relevant to VLSI applications. The process window for the formation of good quality NiSi films on single crystalline silicon substrate ranges from 400 to 600 oC. The optimal process for the formation of silicide contacted NiSi/p+n junction diodes with a junction depth of 0.3 □ m, is a 30 min furnace annealing at 500 oC, and the leakage current density of the resultant diodes was found to be 12.7 nA/cm2. For the samples of Ni/(doped) poly-Si/SiO2/Si structure, thermal annealing in furnace for 30 min at 500 oC or RTA annealing for 1 min at 450 oC resulted in a NiSi-polycide MOS capacitor of optimum I-V characteristics and charge-to-breakdown. For the NiSi/p+n shallow junction diodes fabricated using implant through silicide scheme, BF2+ implantation at 60 KeV to a dose of 1x1015 cm-2 followed by a 30 min 700 oC furnace anneal resulted in NiSi/p+n shallow junction diodes having a junction depth less than 0.15 □m and with the reverse bias leakage current density as low as 20 nA/cm2.