選擇性液相沉積氧化膜在超淺接面矽化鎳製程之應用

Abstract

本論文主要是研究選擇性液相沉積氧化膜在超淺接面矽化鎳製程之應用。首先，我們研究矽化鎳在不同的基板上的行為, 而基板包括了單晶矽、複晶矽、非晶矽及非晶狀複晶矽基板。我們發現在單晶矽及非晶狀複晶矽上，以200 Å厚的鎳在400℃與650℃快速熱回火處理形成的矽化鎳顯示了穩定且較低的片電阻。經由矽化鎳在複晶矽、非晶矽和非晶狀複晶矽上的掃瞄式電子顯微鏡圖片觀察及不同線寬的片電阻量測，我們發現了深色斑點或結塊的出現會嚴重的影響矽化鎳的片電阻。所以，在這些不同的基板上以快速熱回火形成矽化鎳的最佳製程溫度範圍是從400℃到550℃。對於較薄的矽化鎳，它的片電阻值較高且製程溫度變窄。接著，我們藉由第二次的快速熱回火處理及較長時間的600℃爐管回火的方式來測試鎳矽化物的熱穩定性。經由較長時間的回火處理，在非晶矽上的矽化鎳有較好的熱穩定性且幾乎維持相同的片電阻。但在單晶上的矽化鎳，鎳會持續的擴散並造成片電阻的增加。與柱狀複晶矽做比較，以相同的熱處理後，矽化鎳在非晶狀複晶矽上較為穩定。 然後我們利用最佳的條件製作矽化鎳n+/p 超淺接面二極體。我們發現漏電流隨著矽化鎳形成溫度的增加而減少。這是由於矽化鎳完全形成所致。我們也發現漏電流會隨著鎳的厚度增加而增加，這個現象導因於矽化鎳的厚度靠近接面的空乏區。我們也研究各種接觸孔數目的漏電流，它顯示了接觸孔越多，漏電流會越大。 最後，我們開發了選擇性液相沈積的製程來製作接觸孔。這是種在沒有電漿環境下的技術。與傳統活性離子蝕刻製程做比較，選擇性液相沈積顯示了較均勻且較低的漏電流分佈。根據這些結果，我們相信選擇性液相沈積在未來先進元件製作上是極可行的技術。

This thesis studies the application of S-LPD to ultra-shallow junction and nickel silicide process. First, we investigated the sheet resistance behavior of Ni silicide on different substrates including crystal Si (c-Si), polycrystalline Si (poly-Si), amorphous Si (a-Si) and a-poly Si. We found the planer NiSi formed with 200 Å thick Ni on c-Si and a-poly Si is stable and shows low sheet resistance between 400℃ and 650℃ RTA. From the SEM micrographs observation and the line-width sheet resistance measurement of NiSi on poly-Si, a-Si, and a-poly Si, we found the appearance of dark spots or agglomeration would affect the sheet resistance of Ni silicide seriously. So the optimum process window of NiSi RTA temperature on different substrates is ranging from 400℃ to 550℃. For the thinner NiSi, the sheet resistance becomes high and narrows the process window. Next, we tested the thermal stability of Ni silicide by using the 2nd RTA and longer-time furnace annealing at 600℃. Ni silicide on a-Si owns the best stability which remains almost the same sheet resistance for longer time annealing. But for NiSi on c-Si, Ni will continuous diffuse and cause the sheet resistance to increase. Compared to the columnar poly silicon (poly-Si), the non-columnar poly silicon (a-poly Si) is more stable in the same thermal treatment. Then we used the optimum condition to fabricate the nickel silicide n+/p ultra-shallow junction diodes. We found that the leakage current decrease with the increasing silicide formation temperature. This is due to the complete formation of nickel silicide. We also found that the leakage current increase with the increasing of nickel thickness. This phenomenon results from the approach of nickel silicide to junction depletion region. The contact-hole numbers have also been checked for investigation. It shows that the more the contact-hole numbers, the larger the leakage current. Finally, we have developed a novel S-LPD process for contact-hole formation. This technology was performed under a non-plasma environment. Compared to conventional RIE process, the S-LPD process shows uniform and low leakage current distribution. According to the results, we believe the S-LPD process will be the promising technology for future advanced device fabrication.