1394 實體層積體電路之設計與驗證

Abstract

隨著資料傳輸速率在電腦和消費性電子上快速的增加, 我們需要一個不昂貴而且能高速地連接數位裝置的方法. 大多數多媒體消費性電子的設計者都同意IEEE 1394 在未來是連接數位裝置的好選擇. 本論文提出一個IEEE 1394實體層電路的設計. 它包含了實體層-連接層介面, 仲裁控制器, 實體層暫存器､計數器､解碼器､編碼器､雙絞線埠與鎖相迴路電路. 包含雙絞線埠和鎖相迴路電路的類比部分是使用行為模型來模擬. 其他部分則是用可合成的暫存器傳遞層次硬體描述語言所寫. 我們的實體層支援了大多數IEEE 1394實體層的功能, 包含自動組態設定､傳送與接收封包､暫存器讀寫和由IEEE 1394a所定義的仲裁增進. 我們也分析了IEEE 1394的bus 使用效率,並提出一些建議來改善bus效率. 最後我們提出一個IEEE 1394 bus系統的驗證環境. 此驗證環境包含了一個文字的命令檔案, 檔案輸出輸入的引擎, 連接層模型與實體層. 在IEEE 1394 bus 上的兩個裝置間的操縱行為將可在此驗證環境下被驗證. 模擬結果也在本論文中被提出.

With the rapidly increasing data transport rate on computer and consumer electronics, an inexpensive and high-speed method of interconnecting digital devices are needed. Most multimedia consumer electronics designers would agree that IEEE 1394 is a good candidate for interconnecting interface between digital devices in the future. In this thesis, an IEEE 1394 PHY design is presented. It includes PHY-Link interface, arbitration controller, PHY register, timer, decoder, encoder, twisted pair ports and PLL. The analog blocks including twisted pair ports and PLL is designed using behavior model. The other parts are coded in synthesizable RTL Verilog HDL. Most functions of the IEEE 1394 including auto-configuration, transmit and receive packet, register read/write and the arbitration enhancement defined by IEEE 1394a are supported. We also analyze the IEEE 1394 bus efficiency and state some suggestions for improving bus efficiency. Finally, a verification environment for IEEE 1394 bus system is proposed. The verification environment consists of text command file, fileio engine, link layer model and PHY. The operations between two devices on the IEEE 1394 bus are verified under this verification environment. Simulation results of our PHY core are also given in this thesis.