高速串列介面設計與實現- 例 IEEE 1394

Abstract

本篇論文介紹了如何設計與實現高速串列介面，並以IEEE 1394為例。從架構、邏輯方塊與IP設計皆有詳細的討論。此外，我們也提出了一個新的動態緩衝管理方法，藉由此法，可以有效率的共享傳輸與接收的FIFO，增加傳輸的效率。 本篇論文中，以我們所提出的設計流程實現的IEEE 1394，經過模擬之後，可以以400Mbps傳輸資料，並且符合IEEE 1394 1995以及1394a標準的規範。此外，整個IC的實現利用TSMC 0.35 CMOS 1P4M的製程，整體的電晶體閘數大約36K。

This thesis presents the design and implementation of a high-speed serial bus - like IEEE 1394. From architecture, logic blocks to IP (intellectual property) packaging, all the design issues have been exploited. The detail of 1394 IP design is also described. In this thesis we also propose a novel dynamic buffer management that will effectively shares the same memory space in the receiving and transmission FIFO. The simulation results show that 1394 design can operate up to 400 Mbps in data transfer. As the result, the design meets the requirement of 1394-1995 specification and 1394a. The IC implementation is also done by TSMC 0.35 CMOS 1P4M process. The gate count of design is about 36K. 1.1 INTRODUCTION OF SERIAL BUS 1.2 BENEFITS OF HIGH SPEED SERIAL BUS 1.3 OUTLINE OF THIS THESIS CHAPTER 2 CHARACTERISTICS AND COMPARISON OF HIGH SPEED SERIAL BUS 2.1 CHARACTERISTICS OF HIGH SPEED SERIAL BUS 2.1.1 Encoding Method 2.1.2 Topology 2.1.3 Multi-phase 2.1.4 Transaction Mode 2.1.5 Other Characteristics 2.2 COMPARISON 2.3 INTRODUCTION OF IEEE 1394 2.3.1 Primary Characteristics 2.3.2 Topology 2.3.3 Addressing 2.3.4 Protocol Architecture 2.3.5 Subactions 2.3.6 Cycle Structure 2.3.7 Cable Configuration 2.3.8 Arbitration Scheme CHAPTER 3 THE DESIGN FLOW AND TEST METHODOLOGY FOR HIGH SPEED INTERFACE 3.1 THE DESIGN FLOW FOR HIGH SPEED INTERFACE 3.1.1 C-model Simulation 3.1.2 Timing Budget 3.1.3 Behavior Simulation in Verilog Model 3.2 THE TEST METHODOLOGY 3.2.1 Command File Test Methodology 3.2.2 Verification Strategy 3.2.3 Test Environments CHAPTER 4 IEEE 1394 LINK AND PHYSICAL LAYER DIGITAL DESIGN 4.1 THE FUNCTIONS OF LINK AND PHYSICAL LAYER 4.2 ARCHITECTURE DEFINE 4.2.1 Data Path Design Issue 4.2.2 Data Width Issue 4.2.3 Flexible Port Issue 4.2.4 Architecture 4.3 BLOCK DESCRIPTIONS OF FUNCTIONAL BLOCK 4.3.1 Description of Functional Blocks in PHY 4.3.2 Description of Functional Blocks in Link Layer 4.4 DESIGN OF EACH FUNCTIONAL BLOCKS 4.4.1 The Design of Encoder/Decoder and Port Controller 4.4.2 The Design of Arbitration Controller 4.4.3 The Design of Receiver and Transmitter 4.4.4 The Design of CRC Generator and Checker 4.4.5 The Design of Link Controller 4.4.6 Design of FIFO Controller 4.4.7 The Design of Microprocessor Interface and High Speed Data Interface 4.4.8 The Design of Control and Status Register CHAPTER 5 DYNAMIC BUFFER MANAGEMENT METHOD 5.1 MOTIVATION 5.1.1 Different FIFO Management 5.1.2 Performance of Shared Buffer Method 5.1.3 The Problem of Shared Buffer 5.2 DYNAMIC BUFFER MANAGEMENT 5.2.1 Space-Table Method 5.2.2 The Concept of Double-linking List Method 5.2.3 Base Elements 5.2.4 Primary Actions 5.2.5 Algorithm 5.2.6 Realization of Dynamic Buffer Manager 5.3 SUMMARY CHAPTER 6 IMPLEMENTATION AND SIMULATION RESULT 6.1 ASIC IMPLEMENTATION 6.2 TEST PATTERNS AND CHECKLISTS 6.2.1 Test Patterns 6.2.2 Checklists 6.3 THE SIMULATION RESULT 6.3.1 Bus Configuration 6.3.2 Data Decoding and Encoding 6.3.3 Bus Arbitration 6.3.4 Packets and Cycle Structure in the Bus 6.3.5 Interface of Microcontroller and Data Mover 6.3.6 Suspend and Resume CHAPTER 7 CONCLUSION