GSM基頻接收器設計

Abstract

GSM是一個數位化的窄頻分時多工存取（TDMA）通訊系統，其基頻接收端的資料傳輸速率是每秒270.83 k，提供給八個使用者，每個使用者有每秒33.85 k的頻寬。 本篇論文提出一個GSM的基頻接收器。它包括一個相關器（correlator）、等化器（equalizer）、反間插器（deinterleaving）與解碼器（decoder）。在工作測試模擬環境中提供了完整的頻道模型與GSM的傳輸架構。等化器的特色是具有由直線距離計算的軟式輸出、硬體分享和存活路徑記憶體管理（survivor memory management）使用了追溯（traceback）原理，而同樣也使用於解碼器的設計。整個資料流程模擬了誤碼率（BER）的需求，而這些模組的架構設計也予以實現。未最佳化的等化器閘數大約是13000， 50 MHz時脈的總處理能力為1.5 MHz。

GSM is a digital and based on narrowband TDMA communication system, and data rate is 270.83 kb/s on the baseband receiver, to be time-divided between eight users, each has 33.85 kb/s In this thesis, a baseband GSM receiver was proposed. It consists of a correlator, equalizer, deinterleaving and a decoder. Comprehensive channel model and GSM frame structure are provided for performance evaluation. The equalizer features soft output calculated by Euclidean distance, and traceback theorem would be used for survivor memory management which would also be need for the decoder. The thorough data flow had been simulated for the bit error rate requirements and architecture design for the modules had been down. Gate count for the equalizer without optimization is approximated to be 13000. Throughput represents to be 1.5 MHz under 50 MHz clock.