運用時域方法之10G/s 可適性纜線等化器設計(I)

Abstract

本計畫將針對10Gb/s 銅線通訊系統應用，以標準CMOS 製程技術開發其接收 端之自適性等化器。傳統之頻域分析與設計方式，因其功率偵測器之轉換增益過低， 故其等化器之工作狀態極易受製程、電壓、溫度等變異之影響。然而訊號之速度偵 測本質上亦可運用如斜率偵測、過激偵測、相位偵測等時域技術來取代。有鑑於此， 本計畫將發展新的時域分析方法，以開發高效能之斜率偵測器、過激偵測器、相位 偵測器等設計技術，並發展可以快速鎖定之低功耗架構，以期實現具高可靠度、低 功耗、以及快速鎖定性能之最佳化設計。

The goal of this project is to develop the adaptive equalizer in the receiver front-end for 10Gb/s cable communication applications using standard CMOS technology. Conventional frequency-domain approaches are used to build adaptive equalizers. However, the resulting small conversion gain of the power detector makes the operation of the adaptive equalizer quite sensitive to those undesired PVT variations. Based on time-domain analysis, the speed detection can be realized by using slope detection, overshot detection and phase detection. In this project, one of our targets is to develop time-domain design concepts to build effective slope detector, overshoot detector and phase detector. The second target is to develop possible design topology for fast locking and low power consumption. Combined with those techniques mentioned above, a reliable low-power fast-locking adaptive equalizer can be achieved by the end of this project