使用不易受偏移影響斜率偵測器之具有大輸入動態範圍可適性電纜等化器

Abstract

本論文提出使用斜率偵測器之可適性等化器。此偵測機制可避免使用整流器而造成電路容易受偏移(offset)影響。而斜率偵測器會偵測訊號的斜率資訊用以判斷可適性等化器需要提供多少的增益補償。並且，使用了振幅偵測器及共模準位偵測器，增加可適性等化器所能承受的輸入動態範圍。為了使等化器可以減少功率消耗，提出了使用正迴授概念的等化器。而此可適性等化器使用了65nm CMOS製程做驗證，在1.2伏特的電壓供應器及13.5Gb/s的速度下，可補償20.5dB的通道損耗，並且只消耗了11.2mW的功率。並且在附錄A裡，描述一個使用了0.18μm CMOS製程做驗證的可適性等化器，在1.8伏特的電壓供應器及6Gb/s的速度下，可補償23.3dB的通道損耗，並且消耗了27mW的功率。

The thesis presents adaptive equalizers using the slope detector. The detection mechanism avoids using the rectifiers for decreasing the sensitive of offset. The edge-speed is detected by slope detector to adjust the gain-boost of equalizer. Furthermore, with the help of swing detector and common-mode detector, it extends the input dynamic range of adaptive equalizer. In this work, we proposed the positive-feedback based adaptive equalizer to provide more gain-boost without scarifying the power consumption. This chip can work at 13.5Gb/s data rate, and compensates 20.5dB channel loss at Nyquist rate while consuming only 11.2mW (without output buffer) from a 1.2V power supply in 65nm CMOS technology. Furthermore, in the appendix A, we proposed a 6Gb/s adaptive equalizer using slope detector. It can compensate 23.3dB channel loss from a 1.2V power supply with 27mW power consumption in 0.18μm CMOS technology