多值邏輯電路與運算放大器之合成與障礙模型

Abstract

本論文主旨在研究多值邏輯電路的設計與合成，多值邏輯電路的障礙模型，以及運算放大器之障礙模型。關於設計與合成的部份，吾人提出兩套方法來合成多值邏輯電路，一是混合模式CMOS電路，一是電壓模式CMOS電路，並做成積體電路晶片(IC chip)，以驗證多值邏輯電路設計之可行性。結果顯示吾人所提之兩種方法所合成之電路，比起傳統多值邏輯電路，同時兼具速度快、耗電少和面積小的優點。比起二進位的電路，混合模式CMOS電路在速度差不多的情況下，面積平均可省40%，而電壓模式CMOS電路的動態耗能約為二進位的電路的1/10，且面積平均更可省2/3。此研究證明了混合模式CMOS電路較適合做加法的運算，以及電壓模式CMOS電路較適合於低功率的應用。基於以上的考量，吾人將混合模式CMOS電路之加法器和電壓模式CMOS電路之乘法器透過CIC(晶片製作中心)製作成積體電路晶片，並且測試無誤。 在多值邏輯的測試部份，吾人提出了一套較為合理而且實際的多值邏輯障礙模型，針對所有的曾被提出過的電路予以分析，之後發現，在電晶體層次方面，有電流源不對稱、電流源變化和開關停滯等三種障礙可以描述大部份的障礙行為；在邏輯層次方面，有運算子視窗偏移、常數變化和輸入訊號變化等三種障礙可以描述大部份的障礙行為。根據上述之障礙行為所找出之測試圖樣將比傳統的停滯障礙之測試圖樣更為有效而且合理。 由於多值邏輯乃是介於類比和數位之間的一個運算系統，多值邏輯的測試方法將可被推廣而應用於類比系統的測試，所以此研究亦致力於多值邏輯在類比系統之應用，比如以多值邏輯的運算來實現類比電路之障礙模擬器。因為運算放大器(OP)為類比電路中最重要也是最基本的元件，吾人先對封閉迴路運算放大器之障礙行為進行研究，提出了一套比傳統的障礙模型較為簡便又不失其真實性的新障礙模型，以補偏電壓來描述封閉迴路運算放大器之障礙行為，其中包含有限增益，有限輸入阻抗，以及非零的輸出阻抗。另外，此障礙模型用受限電流來描述許多因速度過快，外接電阻過小或外接電容過大所引起的失常現象。經驗證此模型至少可包含92.5%的驟變型障礙和100%的參數型障礙。針對由封閉迴路運算放大器和非橋式被動原件所阻成之類比電路，使用此障礙模型進行障礙模擬，速度將可增快很多。

This dissertation studies design and synthesis for multiple-valued logic (MVL) circuits, fault models of MVL circuits, as well as the fault model for the operational amplifier. On design and synthesis, two schemes to synthesize MVL circuits are proposed: one is for the hybrid-mode circuits, the other is for the voltage-mode circuits. For both circuits, IC chips were fabricated to demonstrate their functions. The result indicates the MVL circuits synthesized by our methods have all the advantages of higher speed, lower power and smaller area than that synthesized by traditional methods. Compared with the binary circuits, the hybrid-mode circuit under the comparable speed of the binary circuit has 40% area reduction, and the voltage-mode circuit has 60% area reduction but consumes only about one-tenth of the dynamic power. This research demonstrates that the MVL hybrid mode CMOS circuit is more suitable to the addition operation and the MVL voltage mode CMOS circuit is more suitable to the lower power application. Based on the above criteria, a hybrid mode CMOS adder and a voltage mode CMOS multiplier were designed and realized in a chip through CIC (Chip Implementation Center), and their functions were verified through measurement. On the testing of the MVL, a more reasonable and more practical fault model was proposed. Analyzing the proposed circuits, we discover that: at the transistor-level, three faults, i.e., current mirror mismatch, current source variation and switch stuck-at faults can describe the faulty behavior of the MVL circuits; and at the logic level, three faults, i.e., literal window shift, constant variation and input variation can describe the faulty behavior of the MVL systems. The test patterns derived from the above fault model are more effective and reasonable than those derived from the traditional stuck-at fault model to test the MVL circuit. Since an MVL circuit can be viewed as an intermediate circuit between a binary circuit and an analog circuit. The practice adopted in testing of the MVL circuit can be considered to be applied to testing the analog circuit. This dissertation also studies the application of the testing of MVL circuit to the testing of the analog circuit, such as the analog fault simulation based on the MVL simulation. Since the operational amplifier (OP) is the most primitive and important building element for an analog circuit, hence, the faulty behavior of the closed-loop OP was first investigated and then a new fault model which is much simpler but without losing its validity than the traditional fault model is proposed. The proposed fault model is an offset fault model which lumps the finite gain, finite input resistance and the non-zero output resistance into an input offset of the OP which is considered to be an ideal. Moreover, the fault model also contains elements which is the limited-current fault to describe the output distortion of the OP when too large a current is required to be drawn from the OP due to too small an external resistance or too large an external capacitance is connected to the OP or a signal of too a high speed is applied to the OP. This offset fault model is verified to be able to cover 92.5% catastrophic faults and 100% parametric faults. For this fault model, when used in fault simulation for the linear analog circuits composed of closed-loop OPs and non-bridged type passive elements, much faster speed improved can be obtained.