超薄閘極氧化層之P型金氧半電晶體中硼穿透暨電漿充電損害效應之研究

Abstract

超薄閘極氧化層之P型金氧半電晶體中硼穿透 暨電漿充電損害效應之研究 研究生:林靖乾 指導教授:施敏博士 國立交通大學 電子研究所 摘要 對於深次微米尺寸的互補式金氧半電晶體(CMOS) ,使用p型複晶系閘(polysilicon gate)來達成表面通道的p型金氧半電晶體, 變成不可或缺。然而,以硼原子植入形成閘極和源/汲極(source/drain)的p型金氧半電晶體中,硼原子容易穿透閘極氧化層(gate oxide)進入矽基板(Si substrate),並且改變通道濃度造成起使電壓(threshold voltage)飄移和降低氧化層的穩定。再則,為了形成淺接面(shallow junction), 以BF2作為植入(implantation)的種類,但F的存在會增強硼穿透的效應。本篇研究提出防止硼穿透的方法有:在N2O環境中成長閘極氧化層和N2+植入。另外亦有F植入以觀察並證實F對硼穿透效應的增強,發現適量之F植入對於增強硼穿透的效應不明顯並改善氧化層的穩定性。 本篇研究另一項為電漿製程產生的天線效應對以超薄氧化層製作的深次微米元件可靠度之影響。由於電漿中充斥高能量的帶電粒子,所以對半導體元件結構有著潛在性的破壞效應。而日趨複雜的電路接線會成為”收集帶電粒子的天線”。當元件的尺寸及氧化層的厚度縮到深次微米的應用範圍時,天線效應會更為嚴重。 而在以p型複晶系作為閘極的p型金氧半電晶體中,硼穿透會使得天線效應更加明顯;對於40埃厚度的氧化層元件而言,以一般的臨界電壓量測在觀察硼穿透的效應是可行的,而對於天線效應的評估則可能會導致錯誤的結果;藉由萃取閘極電流的量測方式,可以得到硼穿透後的氧化層會使得天線效應增強的結果。

Study of Boron Penetration and Plasma Charging –Induced Damage for p+-Poly Gate on Ultra-Thin Oxides Student: Ching-Chyan Lin Advisors: Dr. S. M. Sze Institute of Electronics National Chiao Tung University Abstract For deep submicron CMOS devices, p+-polysilicon gate surface-channel pMOSFETs become indispensable. However, boron atoms implanted into polysilicon gate will penetrate through the gate oxide into Si substrate and alter the channel doping. This causes the instability of threshold voltage and reduces the oxide reliability. To get an ultra shallow junction, BF2 has been employed as an implantation species, but the diffusion of boron atoms from polysilicon gate through thin gate oxide into Si substrate will be enhanced. In this dissertation, we use several methods, such as nitridation and N2+ co-implantation to prevent the boron penetration. We also use F+ co-implantation to introduce into p+-polysilicon gate and find that appropriate F atoms will work on the extrinsic defects located in the SiO2, which may be the origin of extrinsic mode, and renovate these defects, while an intrinsic SiO2 quality is maintained. In addition, this dissertation also investigates the plasma-induced antenna effect on the reliability of device with ultra-thin gate oxides. Plasma processing has become an integral part of the fabrication of integrated circuits. However, it is well known that plasma processing also causes device degradations. Moreover, interconnections on more complex integrated circuits will become antennas to collect the charge imbalance on the wafer surface induced by plasma. For deep submicron CMOS devices with ultra-thin oxide, the antenna effect will be more serious. Using traditional methods of monitoring transistor parameters for detecting plasma-induced charging damage in ultra thin oxides (e.g., Tox< 4 nm) may be not appropriate. Gate leakage current is found to be a novel and efficient test method. Ig values of devices at wafer center and edge have significantly increase. These results show that oxide degradation by plasma ashing process is at wafer center and edge. Besides, N2O oxide has not degraded significantly at wafer center and edge, especially AAR increases to 60K. This implies that using N2O oxide can suppress plasma-induced charging damage due to maintained good quality of dielectric. For the p+-polysilicon gate in surface-channel pMOSFETs, boron penetration will cause oxide integrity degradation. By Ig measurement, we find that BF2 implantation shows larger increase magnitude than B+ implantation, especially for the largest antenna and the highest thermal budget, even increasing to μA magnitude. Thus, we conclude that the plasma-charging induced damage will aggravate.