低溫複晶矽薄膜電晶體之研究

Abstract

低溫複晶矽薄膜電晶體之研究 學生: 吳子建 指導教授: 施敏 博士 國立交通大學 電子工程學系 電子研究所碩士班 摘要 近幾年來，已經提出許多技術來改善低溫複晶矽薄膜電晶體的特性及降低製程的溫度。在本論文裡，我們使用電漿輔助化學氣相沉積的TEOS氧化層而非傳統的低壓化學氣相沉積的TEOS氧化層來當作薄膜電晶體的閘極氧化層。藉由電漿的輔助，TEOS氧化層可以在三百度的低溫下沉積。 在本論文中，我們研究這種低溫薄膜電晶體的電性及可靠性。我們發現這種薄膜電晶體擁有不錯的電子遷移率(37 cm2/V.s)及較低的漏電電流。但是，我們也發現較差的氧化層特性導致在低汲極電壓時，漏電電流主要是受到氧化層漏電電流的支配。除此之外，在以氨氣的電漿處理後，雖然將一些通道上的陷阱鈍化了。但是，電漿輔助化學氣相沉積的TEOS氧化層在高功率的電漿處理下，將會造成一些鍵結的破壞，導致產生一些帶負電的氧化層電荷來增加漏電電流。而在可靠性方面，我們發現有兩種不同的類型的缺陷產生，每一種都分佈在閘極氧化層中不同的位置上。如果應力測試是操作在線性區域，那麼所產生的缺陷是均勻地分佈在整個閘極氧化層中。若是應力測試是操作在飽和區域，那麼他除了產生前面所說的那種缺陷以外，還產生了另外一種熱載子所造成的缺陷。 總而言之，由我們量測求得的電性及可靠性看來，以電漿輔助化學氣相沉積的TEOS氧化層來當作薄膜電晶體的閘極氧化層，仍然是一個相當不錯而且可行的技術。

Study of Low-Temperature Polycrystalline Silicon Thin-Film Transistors Student: Tze-Chien Wu Advisor: Prof. S. M. Sze Institute of Electronics National Chiao Tung University Abstract Although the best device and circuit performances have been reported for TFTs fabricated using a high temperature (typically 950。C or above) process, such devices require costly quartz substrates. On the contrary, low temperature technologies (maximum processing temperature 600。C or below) allow cheaper glass substrates to be used. However, the inferior device characteristics may limit the amount and complexity of the peripheral circuits. Recently, several key technologies that have been proposed to improve the performances of low-temperature TFTs and lower the process temperature. In my thesis, we used PECVD TEOS-SiO2 rather than the conventional LPCVD TEOS-SiO2 as the gate insulator. The PECVD TEOS-SiO2 can be deposited at a temperature of 300。C by utilizing plasma assistance. In my thesis, we investigated the performance and reliability of such kind of low-temperature TFTs. We discovered that it could offer adequate performances, such as low leakage current and m=37 cm2/V.s for many display peripheral circuits. We found that the leakage current at low drain voltage exhibited a different mechanism from that of high-temperature TFTs. Besides, after the NH3 plasma treatment, the trap states in the channel were passivated. However, because of worse endurance of high power plasma, many negative fixed oxide charges were trapped in the PECVD TEOS oxide to increase leakage current. On the reliability, we found that there were two types of stress-induced defects, each with a different position within the gate insulator. Stressing under linear regions produced defects across the whole gate insulator, uniformly distributed from the source side to the drain side. Stressing under saturation regions resulted in additional defects near the drain side. This result of the asymmetric behavior is attributed to the presence of hot carriers. In summary, from the results above, we found that the low-temperature TFTs with PECVD TEOS-SiO2 as the gate insulator could provide good performances and reliability. Therefore, it could be a promising method for forming gate insulator of low-temperature poly-Si TFTs.