具備新穎ONO堆疊式閘極介電層之高效能低溫複晶矽薄膜電晶體製作與特性研究

Abstract

傳統低溫複晶矽薄膜電晶體使用電漿輔助化學氣相沉積系統(PECVD)沉積之TEOS oxide或Si3N4為其閘極介電層，此種低溫介電層含有非常多的缺陷與極低之崩潰電壓，常常造成低溫複晶矽薄膜電晶體的電特性與可靠度不佳。因此，製作低溫高品質的閘極介電層，以提升低溫複晶矽薄膜電晶體製程的電特性是迫切需要的技術。本論文中，我們提出具備新穎ONO堆疊式閘極介電層結構之低溫複晶矽薄膜電晶體，以ONO堆疊式閘極介電層系統分三段製程步驟連續成長此ONO (TEOS Oxide/Si3N4/N2O-plasma Oxide)堆疊式介電層結構。首先，以PECVD N2O電漿成長約30Å之高品質超薄氧化層，再接著堆疊400Å之Si3N4，最後再沉積70Å之TEOS氧化層，完成此新穎ONO (TEOS Oxide/Si3N4/N2O-plasma Oxide) 堆疊式閘極介電層之製作。由電性研究顯示，使用此ONO堆疊式閘極介電層的低溫複晶矽薄膜電晶體比傳統TEOS氧化層低溫複晶矽薄膜電晶體具有更佳的元件電特性及可靠度，以及較低的複晶矽通道缺陷密度，此乃因N2O電漿成長的高品質超薄氧化層與複晶矽形成平坦並有極強Si≡N鍵結的界面，並且成長過程中的N2O電漿鈍化機制 (passivation) 引致大量的氮原子與氧原子修補複晶矽的缺陷所造成的改善。此外，ONO介電層結構中的Si3N4層具有比SiO2高之介電常數，則進一步的提升低溫複晶矽薄膜電晶體之驅動電流，然而PECVD Si3N4可能含有大量的缺陷，且Si3N4易與上層複晶矽閘極的形成不佳的界面，所以我們的ONO結構中設計沉積上層的薄TEOS氧化層，以改善與多晶矽閘極的界面缺陷。 另外，我們利用氨氣 (NH3) 電漿處理，進一步填補降低複晶矽薄膜電晶體的通道缺陷。我們發現氨氣電漿處理可以大幅的改善薄膜電晶體的電特性，尤其對載子移動率 (carrier mobility)、開關電流比 (On/Off current ratio) 及元件可靠度方面的改善效果卓越，這歸功於矽原子與氨氣中的氮/氫原子形成鍵結(Si-N/Si-H)，而填補在通道中grain boundaries和複晶矽薄膜與閘極介電層介面間的dangling bond。 為了更進一步提升元件的電特性，我們將新型ONO堆疊式閘極介電層運用於凹陷式通道 (Recessed-Channel) 結構的薄膜電晶體中，源極和汲極的厚度較通道墊高500Å 之poly-Si薄膜，讓通道的厚度較薄而形成凹陷處。這樣設計的好處是，在凹陷通道區上，當使用準份子雷射結晶技術時，可橫向成長出較大的晶粒，使得載子移動率大幅增加，進而提升元件的驅動電流能力。此外，由於源極和汲極位於較厚的區域，可降低串聯電阻，使得元件特性得到進一步的改善。

Traditionally, low temperature polycrystalline silicon thin-film transistors (LTPS TFTs) were fabricated with PECVD TEOS oxide or Si3N4 as gate insulator. However, the poly-Si TFT with such low quality dielectric films shows poor electric characteristics and reliability due to a large amount of defects and traps in the PECVD TEOS oxide or Si3N4 films. Therefore, a new low temperature process of making high-quality gate dielectric film is necessary for fabricating high performance low-temperature poly-Si TFTs. In this thesis, low-temperature poly-Si TFTs with a novel ONO stack dielectric structure (TEOS Oxide/Si3N4/N2O-plasma oxide) in-situ grown by plasma-enhanced chemical vapor deposition (PECVD) system were presented. The ONO stack gate dielectric structure is composed of bottom layer N2O-plasma grown 30Å ultrathin oxide, middle layer 400Å nitride film and top layer 70Å TEOS oxide. It is found that low-temperature poly-Si TFTs with a novel ONO stack dielectric structure have superior electrical properties, more remarkable reliability and lower interface trap density than traditional TEOS oxide ones. These improvements were attributed to the high quality N2O-plasma grown ultrathin oxide forming smoother surface and strong Si≡N bonds at the oxide/polysilicon interface. In the other hands, N2O plasma passivation effect induces large amount of nitrogen and oxygen atoms passivated the traps in the polysilicon grain boundaries. Furthermore, the middle layer nitride film which has higher dielectric constant than silicon dioxide results in promoting the driving current of poly-Si TFTs. However, the nitride/poly-Si gate interface was not so good as respected and thick nitride film maybe includes a large amount of defects. So we deposited a thin 70Å-thick TEOS oxide as upper layer in our novel ONO structure to improve the interface between gate dielectric and poly-Si gate. In the other way, we further utilized ammonia (NH3) plasma passivation method to promote electrical characteristics of poly-Si TFTs. NH3-plasma passivation can improve enormously the poly-Si TFTs performances, particularly in carrier mobility, on/off current ratio, and reliability. The improvement can be attributed to the nitrogen pile-up at gate dielectric/poly-Si interface and the strong Si-N/Si-H bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films. In order to further promote the device electrical characteristics, we used the ONO stack gate dielectric on new recessed-channel structure TFTs (RC-TFTs). This recessed-channel structure was formed by the thick source/drain regions and the thin channel region. The advantage of RC-TFTs structure is the lag of solidification in thin regions generates lateral thermal gradients and urging grains to grow longitudinally from the thick S/D regions to the thin channel region along the channel when using excimer laser crystallization to recrystallize the ploy-Si films. This kind of grain configuration improves the field effect mobility and results in promoting the device driving current. In addition, since the thickness of source/drain regions can be made thicker, the series resistance of these devices will not increase significantly, and device performance can be further improved.