125 MHz 10 位元之 CMOS 數位發射器

Abstract

本篇論文是在描述一個工作在 3.3伏特, 時脈頻率最高可達125MHz 之 CMOS 數位發射器. 它主要包含兩個部分: (1)10位元, 125MHz之數位類比轉換器 (Digital to Analog Converter), (2)全差動電流迴授模式之傳輸線驅動器 (Line Driver). 本數位發射器是採用 TSMC 0.35mm SPQM CMOS 之製程來實現. 就數位類比轉換器而言, 為能達到高速之要求, 故採取電流切換模式之架構. 此外, 為能有效降低突波 (Glitch Energy), 及差動非線性誤差 (Differenital Nonlinearity Error), 故採用一個等效於 8 位元之 Thermometer 解碼架構. 它是由四個 8x8 的電流單位矩陣 (Current Cell Matrix) 所組成, 每一個矩陣有 63 個電流單位是由 B9 至 B4 6個最高位元所控制, 所以四個矩陣總共會多出四個電流單位, 我們只需取其中三個電流單位來由 B3 和 B2 所控制. 故可以說, 255 個相同的電流單位分別由 B9 至 B2 這 8 個位元來控制. 它具有等效於 8 位元之 Thermometer 解碼架構, 但在實際解碼上, 卻只具有 6 位元Thermometer 解碼之複雜度. 至於 B1 和 B0, 則直接採取二進位制之簡單架構來做. 而就傳輸線驅動器而言, 它是採取全差動 (Fully Differential) 架構, 並使用電流迴授模式之方法, 以達到閉迴路頻寬能大於 100MHz, 而其轉動率 (Slew Rate) 亦能超過1000V/ms. 在 3.3V 工作電壓下, 它能驅動一個 10MHz, 4.7Vpp 之 sine 弦波於 50Ω 之負載, 而其 THD 值為 -38dB. 其靜態功率約為 39mW, 而其輸出之功率效益則約為 58%. 本數位發射器包含 Pads 之晶片面積為 2200mm x 2200mm, 電源電壓為 3.3V, 晶片最大消耗功率為 160mW.

This thesis describes the design of a 3.3V 125MHz CMOS digital transmitter, which is composed of a 10bit, 125MHz digital to analog converter and a fully differential current-feedback line driver. The digital transmitter had been fabricated with a TSMC 0.35mm SPQM CMOS technology. To achieve the need for high speed, the digital to analog converter is based on current switch mode architecture. Besides, to effectively lower the glitch energy and differential nonlinearity, the DA converter is implemented in segmentation as if 8 bits thermometer decoder architecture. It is composed of four 8 x 8 current cell matrices, and there are 63 current cells controlled by B9 to B4, the 6 MSB bits, in each matrix. The total four matrices will have four redundant current cells, and three out of these four current cells will be controlled by B3 and B2. So there are total 255 the same current cells controlled by eight MSB bits. The eight MSB bits are decoded with the simplicity of a 6-bit thermometer decoder but as if equal to the architecture of 8-bit thermometer decoder. The remaining B1 and B0, the two LSB bits, are simply implemented by two binary weighted current sources. The line driver has a fully differential architecture and uses current-feedback approach to achieve the closed-loop bandwidth in excess of 100MHz, and also the slew rate is higher than 1000V/ms. It can drive a 10MHz, 4.7Vpp sine-wave across a 50Ω load from a 3.3V power supply with a THD = -38dB. The quiescent power consumption of the line driver is 39mW while the export power efficiency is about 58%. The digital transmitter area inclusive of pads is 2200mm x 2200mm. The biggest total power consumption is 160mW from 3.3V power supply.