寬頻數位頻率合成器及其應用之研究

Abstract

隨著CMOS製程的快速演進，超大型積體電路的設計趨勢朝向了單晶片系統設計發展。在單晶片系統設計□，設計的方法、成本和時間是最主要必需考量的議題。智慧財產的概念於是被提出來以符合單晶片系統設計的要求。在數位頻率合成電路智慧財產的基礎下，我們提出了一個可以應用在無線通信網路的寬頻的數位頻率合成電路並可達成降低成本和縮短設計週期的目標。為了達到系統的要求和產生900MHz和2.4GHz的高頻頻率，我們利用全客戶的設計方法來完成其中的壓控震盪器。 為了解決數位頻率合電路的控制器和壓控震盪器之間的界面問題，並提供數位到電壓的轉換功能，我們也設計了一個數位電壓轉換電路。這個數位電壓轉換電路是一個以標準元件庫為基礎的新穎設計，全部以標準元件庫中最常見的反相器和三態反相器來達到數位電壓轉換的功能。這種以標準元件庫為基礎的設計方法，提供了一個低成本和高度可移植性的數位對電壓轉換的解決方案。 我們使用了0.35mm SPQM CMOS 的製程來實現這個寬頻的數位頻率合成器。量測的結果顯示，壓控震盪器的輸出可以從136MHz到1.981GHz。另外，在震盪器輸出頻率為256MHz時，頻率抖動的峰對峰值是403ps，均方根值是85.6ps，而數位電壓轉換器的解析度可達0.32mV。 最後，我們根據寬頻數位頻率合成氣的架構，提出一可工作於1.8GHz直接轉換的差編碼正交相位移動鍵。除了可以達到原先寬頻數位頻率合成器的特性外，並可以直接輸入基頻的I和Q的信號將以編碼並選擇適當的輸出相位。使得此數位頻率合成電路的控制器的應用更加地實用和有彈性。這的確增進了單晶片系統的設計效率並縮短了設計的時間。

With the rapid advance in CMOS technology, the trend of the VLSI design is then towards system-on-chip (SoC) where design methodology, cost, and turnaround time are major issues. Concepts of intellectual property (IP) are then proposed to fit for SoC designs. Based on a digital frequency synthesizer (DFS) controller IP, the wideband digital frequency synthesizer is proposed to fit in with the wireless LAN (local area network) applications, which provides low cost and efficient design periods. A full-custom voltage-controlled oscillator (VCO) is designed to achieve the system requirements and generate such a high-speed frequency. In order to solve the interface between the DFS controller IP and the VCO and provide a digital-to-voltage conversion, a novel cell-based digital-to-voltage converter (DVC) is proposed, too. This DVC only uses inverters and tri-state inverters, which are common and various elements in a cell library. The cell-based manner gives a low-cost and portable design methodology of the digital-to-voltage conversion. The wideband digital frequency synthesizer is fabricated in TSMC 0.35 mm single-poly-quadruple-metal (SPQM) CMOS technology. The measurement results show that its output bandwidth is from 136 MHz to 1.981 GHz and has a peak-to-peak jitter of 403 ps with root-mean-square (RMS) value of 85.6 ps @256 MHz. The DVC resolution can achieve 0.32 mV. At last, a 1.8 GHz direct-convert DQPSK transmitter is proposed based on the architecture of wideband digital frequency synthesizer. The post-layout simulations show it not only achieves the properties of wideband digital frequency synthesizer but also chooses the proper output phase from baseband inputs, I and Q. This makes the application of wideband digital frequency more flexible and practical. It also reduces design turn-around time and increases efficiency in the SoC design indeed.