應用於數位電視調諧器升頻電路之研究

Abstract

本論文旨在利用CMOS製程實現規格符合數位電視調諧器的升頻電路，其電路包含有寬頻高線性度低雜訊放大器、混波器及頻率合成器電路，能夠接收頻率範圍50MHz ~ 860MHz的射頻電視訊號後，提升至1220MHz中頻。本地振盪源採用低相位雜訊的電感電容交叉耦合式振盪器並以兩組切換電容完成四頻段可調範圍來涵蓋頻率1270MHz ~ 2080MHz的本地振盪源訊號。此升頻電路設計採用TSMC 0.18um 1P6M製程，其電壓增益約25.4dB，雜訊指數為9.1dB以下，輸入反射損耗至少18dB以上、IIP3為30dBmV。

The purpose of this paper is to implement a CMOS Up-Conversion circuit for Digital TV tuner applications. The circuit consists of wide band and high linearity LNA, mixer, and frequency synthesizer. The channelized TV signals from 50 MHz to 860 MHz are up-converted to a 1220 MHz intermediate frequency by a wide band synthesizer. The local oscillator in the synthesizer is realized by adopting low phase noise LC-tank cross-coupled VCO. Four bands with two controlled bits are used to cover the operating bands from 1270 MHz to 2080MHz. This up-converter is manufactured by TSMC 0.18um 1P6M process. The performances with voltage gain 25.4 dB, noise figure less than 9.1 dB, input return loss more than 18 dB, and IIP3 about 30 dBmV are expected.