應用於行動電視標準之射頻電路及系統

Abstract

本篇論文主要探討手持式行動射頻調諧器於系統層級及電路層級，實現考量之解決方案。本文針對詳細之設計流程(以地面/手持式數位視訊廣播(DVB-T/H)標準為例)，從標準規格研讀、轉換成射頻接收機規範之考量及推導、再切分成細部電路方塊之實現要求，做一完整呈現。三個高整合性射頻調諧器已實現於先進CMOS製程以驗證系統設計概念之完善程度。三個實驗晶片皆採用直接降頻架構，以期達成最高之整合性及硬體共享程度。 第一個高整合性調諧器晶片設計實現於 0.13μm CMOS 製程。此射頻調諧器包含射頻前端電路、類比基頻電路、及頻率合成器，並支援雙頻帶之操作。射頻前端電路包含一創新之單端轉雙端之低雜訊放大器，及一電流切換模式之可變增益技巧，以期可達成最佳之訊號－雜訊/干擾比。為了實現一低電壓操作、低功率消耗、及高整合性之射頻調諧器設計，許多電路設計技巧被巧妙使用、並於本文中仔細討論描述。此接收機在單一1.2伏特操作下，可達成-96.7dBm之接收敏感度，連續操作模式下整體電路功耗為114毫瓦。 第二個高整合性調諧器晶片設計實現於 65nm CMOS 製程。此射頻調諧器整合一創新之可支援單端及雙端輸入之低雜訊放大器，以適合發展單端輸入(低成本,RF單晶片)或雙端輸入(高抗雜訊干擾,適用系統單晶片)之解決方案，並降低晶片研發過程再投片的風險。此部分研究同時探討當製程從0.13μm轉換至65nm製程時，RF電路設計必要之考量及挑戰。晶片系統性能驗證流程（含數位解調器）及結果，也詳盡描述於本文中。此接收機在單一1.2伏特操作下，達成-97.3dBm之接收敏感度，連續操作模式下整體電路功耗僅為88毫安培。

This dissertation is focused on system-level and building-block-level solutions in realization of mobile TV tuners. Detailed design procedures starting from standard specifications to receiver specifications to building block requirements is presented, with an emphasis on the DVB-T/H standard. To demonstrate the design aspects, three fully integrated RF tuner prototypes were realized in advanced CMOS technologies. Direct-conversion architecture was used to achieve maximum-level of integration and block sharing. The first prototype was designed and implemented in 0.13μm CMOS technology to meet the specifications of DVB-T/H standard. The tuner supports dual-band operation and includes RF front-end, analog baseband, and frequency synthesizer. The front-end comprises a novel single-to-differential low noise amplifier (LNA) and a novel variable-gain technique to maintain the maximum signal-to-noise-and-interference ratio (SNIR). Techniques to enable low-voltage, low-power, and high-integration tuners are discussed in more details. The receiver achieves a sensitivity level of -96.7dBm and dissipates 114mW from a 1.2 V supply. The second prototype was designed and implemented in 65nm CMOS technology, based on the same architecture. A wideband LNA compatible for differential and single-ended inputs was integrated to meet the requirements either on RF-alone or system-on-a-chip (SoC) developments and to reduce the risks of design re-spin. The description in the second implementation is mainly focused on the specific challenges related to the 65nm CMOS technology. Detailed chip verification is presented, including system-level using a digital demodulator. The receiver achieves a sensitivity level of -97.3dBm and dissipates 88mA from a 1.2 V supply.