一個用於單晶片系統設計上的數位頻率合成電路產生器

Abstract

隨著CMOS製程的快速演進，超大型積體電路的設計趨勢朝向了單晶片系統設計發展。在單晶片系統設計□，設計的方法、成本和時間是最主要必需考量的議題。智慧財產的概念於是被提出來以符合單晶片系統設計的要求。在數位頻率合成電路智慧財產的基礎下，我們提出了一個可以應用在無線通信網路的900MHz頻率合成電路並可達成降低成本和縮短設計週期的目標。為了達到系統的要求和產生900MHz的高頻頻率，我們利用全客戶的設計方法來設計其中的壓控震盪器，它的輸出範圍可以從865MHz到1038MHz。 為了解決數位頻率合電路的控制器和壓控震盪器之間的界面問題，並提供數位到電壓的轉換功能，我們也設計了一個數位電壓轉換電路。這個數位電壓轉換電路是一個以標準元件庫為基礎的新穎設計，全部以標準元件庫中最常見的反相器和三態反相器來達到數位電壓轉換的功能。這種以標準元件庫為基礎的設計方法，提供了一個低成本和高度可移植性的數位對電壓轉換的解決方案。我們也推導了這個數位電壓轉換器的特性方程式，轉換出來的電壓值可以直接由這組方程式來估算，並可達到不錯的精確度。 我們使用了0.6mm SPTM CMOS 的製程來實現這個900MHz的頻率合成器。量測的結果顯示，在輸出訊號除以10的情況下，頻率抖動的峰對峰值是82ps，均方根值是11.8ps，而數位電壓轉換器的解析度可達0.5mV。 最後，我們發展了一個名為CCDFS的程式，可以根據系統的規格自動產生數位頻率合成電路的控制器。此數位頻率合成電路在轉換標準元件庫和新製程時所面臨到的所有問題都包含進程式□面，並可由程式自動解決，使得此數位頻率合成電路的控制器的智慧財產更加地實用和有彈性。這的確增進了單晶片系統的設計效率並縮短了設計的時間。這個程式也可經由網際網路來執行，藉著功能強大的全球資訊網，可提供使用者一個非常友善的界面。

With the rapid advance in CMOS technology, the trend of the VLSI design is then towards system-on-chip (SOC) where design methodology, cost, and turnaround time are major issues. Concepts of intellectual property (IP) are then proposed to fit for SOC designs. Based on a digital frequency synthesizer (DFS) controller IP, a 900 MHz frequency synthesizer is proposed to fit in with the wireless LAN (local area network) applications, which provides low cost and efficient design periods. A full-custom voltage-controlled oscillator (VCO) is designed to achieve the system requirements and generate such a high-speed frequency. Its output frequency range can be from 865 MHz to 1038 MHz. In order to solve the interface between the DFS controller IP and the VCO and provide a digital-to-voltage conversion, a novel cell-based digital-to-voltage converter (DVC) is proposed, too. This DVC only uses inverters and tri-state inverters, which are common and various elements in a cell library. The cell-based manner gives a low-cost and portable design methodology of the digital-to-voltage conversion. Characteristic equations of the DVC are also derived. Output voltages can be then obtained from those equations with good accuracy and efficiency. The 900 MHz frequency synthesizer is fabricated in TSMC 0.6 mm single-poly-triple-metal (SPTM) CMOS technology. The measurement results show that the divided-by-ten output frequency has a peak-to-peak jitter of 82 ps with root-mean-square (RMS) value of 11.89 ps. The DVC resolution can achieve 0.5 mV. At last, a program named CCDFS is developed to automatically generate the DFS controller IP according to system specifications. All issues about the DFS controller IP during cell library transfers and process migrations are considered in this program. This makes the DFS controller IP more flexible and practical. It also reduces design turn-around time and increases efficiency in the SOC design indeed. Web version of CCDFS is also online now, which provides a user-friendly interface and allows users to access via the powerful Internet. List of Figures List of Tables Chapter 1 Introduction 1-1 Motivation 1-2 Thesis Organization Chapter 2 Principles of Digital Frequency Synthesizer 2-1 Frequency Synthesizer Basics 2-2 TDC Based DFS Structure 2-2-1 Jitter Model and Jitter Reduction 2-2-2 Frequency Search Algorithm 2-2-3 TDC Based Architecture 2-2-4 Circuit Design Chapter 3 Design of a 900 MHz Mix-Mode Frequency Synthesizer 3-1 Introduction 3-2 Voltage-Controlled Oscillator 3-3 Cell-Based Digital-to-Voltage Converter 3-3-1 Basic Concepts 3-3-2 Advanced DVC Structure 3-4 Chip Implementation 3-4-1 Design Flow 3-4-2 DVC Circuit Design 3-4-3 Simulation Results 3-4-4 Chip Summary 3-5 Measurement Results Chapter 4 CCDFS - a HDL Generator for DFS Controller 4-1 The Program Interface and Parameters 4-1-1 DFS Parameters 4-1-2 Cell Library Specifications 4-1-3 Input File Formats 4-1-4 CCDFS on the Web 4-1-5 Output Files of CCDFS 4-2 Program Organizations and Flows 4-2-1 Program Organizations 4-2-2 Program Flows 4-3 Program Implementations 4-3-1 The Main Function 4-3-2 The Input Function 4-3-3 The Module Function 4-3-4 The Clock Function 4-3-5 Other Functions Chapter 5 Conclusion and Future Work Reference Appendix A Other Full-Custom Layouts Appendix B Chip Pin Lists Appendix C Synthesis Scripts of the DFS Controller