標題: | Design of a wide-band frequency synthesizer based on TDC and DVC techniques |
作者: | Hsu, T Hsu, TR Wang, CC Liu, YC Lee, CY 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | ADPLL;clock generator;DVC;frequency synthesizer;IP;mixed mode;SOC;TDC |
公開日期: | 1-十月-2002 |
摘要: | A wide-band frequency synthesizer based on time-to-digital (TDC) and digital-to-voltage (DVC) conversion techniques is proposed here. The proposed frequency synthesizer has the capabilities of jitter reduction and large bandwidth, making it more robust for high-frequency applications. A test chip is designed and fabricated in 0.6-mum CMOS single-poly triple-metal process. Here, the novel DVC circuit is realized by tristate inverters, where the resolution can achieve 0.2 mV. Control stability of jitter can improve about 24 dB by exploiting the TDC-based controller. In order to achieve high output frequency and large output range, an analog voltage-controlled oscillator is designed to provide a locked range from 900 to 1900 MHz with < 22 kHz resolution at 3.3 V. Simulation and test results show that the proposal can work as expected. Moreover, the TDC-based controller can be treated as soft IP to speed up turnaround time. |
URI: | http://dx.doi.org/10.1109/JSSC.2002.803011 http://hdl.handle.net/11536/28479 |
ISSN: | 0018-9200 |
DOI: | 10.1109/JSSC.2002.803011 |
期刊: | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Volume: | 37 |
Issue: | 10 |
起始頁: | 1244 |
結束頁: | 1255 |
顯示於類別: | 期刊論文 |