A 125MHz 10位元之 CMOS 全差動取樣並保持電路

Abstract

本篇論文描述一個 3.3V, 125MHz, 10 位元之 CMOS 全差動取樣並保持電路, 它包含一高速運算放大器, 電容以及一些 MOS 開關. 我們所設計之取樣並跑持電路主要是作為高速類比數位轉換器之前端電路. 高速運算放大器之架構乃採用全差動望遠鏡式疊串架構以得到 6 倍的時脈速度 (125MHz)之單一增益頻寬並且 維持 61dB之低頻增益. 全差動取樣並保持電路之架構主要應用相關雙重取樣以及平行處理之想法以消除 運算放大器有限低頻增益所產生之誤差並同時提高輸入信號的頻寬. 當電路操作在時脈速度為 125MHz 時, 10 位元解析度之要求下, 輸入信號頻寬可達到 25MHz. 此全差動取樣並保持電路是使用 TSMC 0.35um 1P4M CMOS 製程技術下線生產. 電源電壓為 3.3V, 晶片面積為 1800 x 1800(um*um). 整個電路最大耗電量為 24.0mW.

This Thesis describes the design of a 3.3~V, 125~MHz, 10-bits CMOS Fully Differential Sample and Hold circuit (S/H), which is to be mainly intended for front-end use in high speed analog-to-digital converters. The S/H is composed of a high speed operational amplifier, capacitors and MOS switches. The fully differential telescopic cascode amplifier architecture is used in our design of the high speed operational amplifier. From the simulation, 61dB DC gain is obtained, and the unity gain frequency of the amplifier is over six times of the clock rate. The S/H architecture uses a correlated-double-sampling scheme to reduce the effects of op-amp offset and finite DC gain, and simultaneous it uses the conception of parallelism to improve the input signal bandwidth. It achieves 10-bits operation up to the 25MHz at the clock rate of 125MHz with fully swing 2V. The S/H has been fabricated with a TSMC 0.35um 1P4M CMOS technology. Total power consumption is 24.0mW from a single 3.3V supply, and the chip area measures 1800 x1800(um*um).