超薄氧化層在金屬閘和多晶矽閘電容中特性的研究

Abstract

當CMOS 閘長度微縮到 100 nm, 其閘氧化層為超薄時，我們遇到了多晶矽空乏效應和高的片電阻。為了解決這些問題，使用金屬閘是一個好方法。我們用氮化鈦做閘極，氧化層或氮化氧化層當作閘氧化層。閘氧化層厚度為4 nm。RTA 溫度分別為500 °C, 600 °C, 700 °C。我們比較氮化鈦閘和多晶矽閘電性上的差異以及研究RTA 溫度對氮化鈦閘電性的影響。 比較氮化鈦閘和多晶矽閘，氮化鈦閘較少有多晶矽空乏效應而且Cinv幾乎等於Cacc 。對於4 nm氮化氧化層而言，和多晶矽閘相比，氮化鈦閘的Cinv / Cacc 有顯著的改善。根據量測的結果，RTA 溫度會影響氮化鈦閘的特性。在不同的RTA 溫度下，RTA 600 °C的氮化鈦閘在崩潰電荷及崩潰電場方面有最好的表現。RTA 溫度也會影響氮化鈦閘的平帶電壓及片電阻。氮化鈦閘的平帶電壓會隨著RTA 溫度增加而往負的方向增加。氮化鈦閘的片電阻隨著RTA 溫度增加而減少。 電漿損害在氮化鈦閘電容器中是很嚴重的。因為在金屬閘製程中多次使用Metal etcher 去蝕刻金屬及灰化光阻。我們研究氮化鈦閘電容器其天線面積比為16,1000和10000的電漿損害效應。天線面積比為10000的電容器有最嚴重的電漿損害。我們也發現晶片中心的元件所受到的電漿損害遠較晶片周圍的嚴重。改善金屬閘製程中的電漿損害情況是刻不容緩的事。 加完偏壓後，在低電場區出現了電應力導致漏電，此漏電流隨著注入的電荷數增加而增加。

Continued scaling of CMOS gate length to 100 nm region with ultra-thin gate oxide, we have problems of poly gate depletion and high gate resistance. To solve these problems, metal gate is a good candidate. We use TiN as gate and oxide or N2O oxide for gate oxide. The gate dieletric thickness is 4nm. RTA temperature is 500 °C, 600 °C, 700 °C, respectively. We compare the difference of TiN gate and poly gate with electric measurements and study the impact of RTA temperature on the electric characteristic of TiN gate. Comparing to TiN gate and poly gate, the TiN gate capacitance has less poly depletion effect and Cinvis near to Cacc.. For the 4nm N2O oxide, TiN gate has significant improvement in Cinv / Cacc compared to poly gate. According to the measurement result, the RTA temperature will affect the characteristic of TiN gate. The metal gate with RTA 600 °C has the best performance in charge to breakdown and oxide breakdown field as compared to those with RTA 500 °C and RTA 700 °C. RTA temperatures also affect the flat-band voltage and sheet resistance of TiN gate. The higher RTA temperature, the more flat-band voltage shift of TiN gate happens. The sheet resistance of TiN gate decreases as the RTA temperature increases. However, the Plasma-induced-charge damage is very serious for TiN gate MOS because it is necessary to use metal etcher for etching metal and ashing P.R. many times in metal gate process. We studied plasma damage of control sample, MOS capacitors with antenna area ratio 1000 and 10000. We found that the capacitors with antenna area ratio 10000 suffered severe plasma damage. The results also showed that the capacitors located at the central region of the wafer suffered more severe plasma damage than those located at the edge region. The improvement of plasma damage in metal gate process is very demanding urgently. Stress induced leakage current appears after the stress at the low field and increases with injected charge.