電漿製程對N通道金氧半場效應電晶體之損害效應

Abstract

在本論文中，我們採用兩種關鍵的電漿製程並且研究電晶體對不同材質的氧化層（即純氧與氮化氧）之損害效應。 首先，我們發現N2O複晶矽再氧化之製程可以抑制逆短通道效應。N2O再氧化層會在高溫製程注入大量的空洞，使得通道摻雜的硼元素擴散能力降低，這會使得源極/汲極表面的硼濃度降低，並導致臨界電壓的變小。除此之外，我們發現複晶矽蝕刻製程會使得閘極氧化層的邊緣受到損傷。過蝕刻的時間越久，接下來的再氧化製程會使得氧化層的邊緣長得比較厚。既然閘極導致之汲極漏電流與閘極邊緣之電場強度有強烈關連，因此複晶矽過蝕刻的時間愈長，就會量到愈小的閘極導致之汲極漏電流。相對的，我們發現崩潰電荷的量測並不能用來檢驗出元件在不同的複晶矽過蝕刻時間上的差異。再者，崩潰電荷的數值也與複晶矽天線元件在晶片上的位置無關。實驗結果也顯示了較長的複晶矽過蝕刻時間的元件比較容易在閘極與汲極或閘極與源極重疊區發生崩潰現象。除此之外，我們也發現過蝕刻時間久的電晶體在做通道熱載子入射實驗中，會有比較嚴重的特性退化。 另一方面，在金屬電漿製程中，我們發現崩潰電荷的量測是一種很敏感的檢測閘極氧化層特性的工具。天線面積比大的元件會有較小的崩潰電荷數值，並且晶片中央的元件也會受到較大的損害。相對的，我們卻發現金屬電漿製程不會對O2或是N2O成長的氧化層或再氧化層產生損害上的差異。在天線元件的熱載子入射實驗方面，我們也發現到天線元件確實有比較嚴重的特性衰退。

In this thesis, the effects of two key plasma processes in transistor fabrication were studied on transistors with their oxide and re-oxidation performed in various ambient (i.e., pure oxide and nitride oxide). First, it is found that N2O re-oxidation process can reduce the reverse short channel effect. If N2O re-oxidation is used, the injection of vacancies during high temperature process will retard the boron diffusion. The boron concentration at the S/D surface will be lower and threshold voltage decreases. In addition, it is found that the poly gate edge is damaged during poly etching process. The thickening of gate oxide at the gate edge increases for longer poly over-etching time. Since GIDL current is strongly dependent on the electric field strength and therefore oxide thickness at the gate edge, its value decreases for devices with longer poly over-etching time. In contrast, no significant trend in Qbd results is found for devices with various poly over-etching time. Furthermore, no significant difference in Qbd is found for devices with different poly antenna devices, i.e., no obvious Qbd dependence on wafer location is found. From our experiments, it is also shown that more breakdown events occur at gate-to-drain/source overlap region for longer poly over-etching time. In addition, devices with longer poly over-etching time depict more severe degradation when channel hot carrier injection is applied. On the other hand, Qbd measurement is found to be a sensitive tool to monitor the effects of metal plasma processing on the characteristics of gate oxide. The Qbd values of antenna devices are low, and devices at the center of the wafer are heavily damaged. In contrast, no difference is found for wafers processed in either O2 or N2O ambient The antenna devices also depict severe degradation when hot carrier injection is applied. Chinese Abstract ………………………………………………………….i English Abstract ..………………………………………………………iii Acknowledgements……………………………………………………...v Contents………………………………………………………………….vi Table Captions…………………………………………………………viii Figure Captions………………………………………………………….ix Chapter 1. Introduction………………………………………………...1 Chapter 2. Experiments and Measurements………………………….5 2.1 The Process Flow of NMOS Transistors………………………..5 2.2 Determination of Gate Oxide Thickness by Fowler-Nordheim J-V Fitting…………………………………………………….8 Chapter 3. The Effects of Poly-Etching Process on Gate Oxide Integrity & Device Characteristics…………….11 3.1 Evaluation of Plasma Etching Damage………………11 3.1.1 Suppression of Reverse Short Channel Effect by N2O Re-oxidation………………………………11 3.1.2 Effects of Gate Etching Damage on Gate Induced Drain Leakage (GIDL) Current…………………………………13 3.1.3 Poly Antenna Effects…………………………………….15 3.2 Effects of Poly Etching-Damage on Breakdown Locations……16 3.2.1 Gate Oxide Breakdown in the Channel Region………….16 3.2.2 Gate Oxide Breakdown at Channel Edge (Source/Drain-to- Gate Overlapped Region)………………………………...18 3.2.3 Relationship between Breakdown Location and Poly Over- Etching Time……………………………………………..19 3.3 Hot-Carrier Stress……………………………………………....19 3.3.1 Device Degradation……………………………………...20 3.3.2 Degradation due to Poly Etching Damage……………….20 Chapter 4. Plasma Charging Effects on Gate Oxide Integrity and Device Degradations……………………………………...22 4.1 Charging Damage Induced Oxide Degradation………………..22 4.1.1 Time Dependent Dielectric Breakdown (TDDB)………..23 4.1.2 Gate Leakage Current……………………………………25 4.2 Hot-Carrier Stress………………………………………………26 4.3 Summary………………………………………………………..27 Chapter 5. Conclusions………………………………………………..29 5.1 Conclusions………………………………………………29 5.2 Future Work………………………………………………31 References………………………………………………………………32