本質非晶/多晶矽薄膜電晶體的新解析模式及分析方法

Abstract

本論文建立了新的解析模式來分析本質非晶矽薄膜電晶體及複晶矽薄膜電晶體的直流電流--電壓特性,並且加以實驗驗證。再者,利用電流--電壓解析模式所賴以建立的基本傳輸機制來分析並探討複晶矽薄膜電晶體的可靠性問題。因為非晶矽薄膜電晶體及複晶矽薄膜電晶體的電性是由不同的物理機制運作所產生,本論文的內容主要分成兩大部分。 在一開始,我們利用第一章做一般的簡介並說明本論文的組織架構。第一部分包含了第二至五章,並且我們把焦點放在本質非晶矽薄膜電晶體的特性分析。第二章介紹非晶矽薄膜電晶體的研究背景並且簡介測試元件的製程及第一部分的組織架構。利用考慮陷入電荷之經驗模式的一維卜松方程式,第三章建立了面電荷密度模式及非晶矽金屬--絕緣層--半導體(MIS)電容的電容--電壓解析模式。利用電容解析模式,陷入電荷的經驗參數可由非晶矽MIS 電容的電容--電壓特性曲線萃取得到。利用面電荷密度模式,第四章建立了非晶矽薄膜電晶體的電流--電壓解析模式。接著,我們利用陷入及自由電子的密度建立了等效遷移率的經驗模式。由萃取到的等效遷移率顯示:只有從準靜態電容--電壓曲線所萃取到的陷入電荷經驗參數,才適用於分析非晶矽薄膜電晶體的直流特性。在電流模式中再考慮源/汲極的寄生電阻效應,非晶矽薄膜電晶體的等效通道長度即可被萃取得到。 為改善在萃取等效遷移率及等效通道長度的過程中所產生的缺失,一個校正迴圈被提出。透過此校正程序,萃取到的寄生電阻值將不隨通道長度而改變,並且僅需要一組參數值,即可準確地模擬不同通道長度之非晶矽薄膜電晶體的轉換特性。第五章摘要說明第一部分的結論。 第二部分包含了第六至九章,並且我們把焦點放在本質複晶矽薄膜電晶體的特性分析及它們的可靠性問題。第六章介紹複晶矽薄膜電晶體的研究背景並且簡介測試元件的製程及第二部分的組織架構。顆粒屏障高度是分析複晶矽薄膜電晶體電性所需考慮的一重要物理量。而在輸出特性曲線於高汲極電壓區所觀察到的kink現象是複晶矽薄膜電晶體另一個顯著不同的特性。第七章一開始藉由把整個閘極電壓範圍分成兩部份來建立顆粒屏障高度的解析模式。當閘極電壓小於VT0時,利用電荷中性及整顆粒完全空乏條件,顆粒屏障高度可表示成顆粒尺寸及顆邊能態密度的函數。當閘極電壓大於VT0時,顆邊能態及閘極電壓間會形成電性耦合,此時顆粒屏障高度可用準二維位能法解卜松方程式得到。利用此建立的解析模式及合理的參數值所模擬出來的結果與實驗值極為吻合。隨後我們根據前面所建立顆粒屏障高度的準確模式,並利用考慮DIGBL效應的介面層熱游離擴散理論,來建立低汲極電壓區的電流--電壓解析模式。當複晶矽薄膜電晶體於高汲極電壓區運作時,藉由假設電子--電洞對的崩潰產生過程只會由來自DIGBL電流的高能量電子所觸發,我們可以建立複晶矽薄膜電晶體的新電流解析模式。使用合理參數所模擬得到的結果,在整個汲極電壓區都與實驗值相當吻合。此模式對不同通道長度的複晶矽薄膜電晶體亦都適用。接下來, 利用前面發展的電流模式,我們可得到電流對溫度關係的解析式。從在不同溫度所測量到的輸出特性曲線顯示:電流於低汲極電壓區呈現正溫度相依現象,而在kink區呈現負溫度相依現象。從Arrhenius plot所得到電流的活化能值亦呈現相同的趨勢。這些現象驗證了我們所發展複晶矽薄膜電晶體的電流--電壓解析模式,其所預測電流的溫度相依趨勢之正確性。第八章致力於探討複晶矽薄膜電晶體的可靠性問題。我們藉由三個特意設計的stress策略來探討額外顆邊能態、介面態及氧化層陷入電荷三種缺陷在衰退特性中的個別效應,並解析複晶矽薄膜電晶體的衰退機制。利用前幾章所研討的電流傳輸機制,複晶矽薄膜電晶體的衰退機制可得到合理的解釋。再者,藉由閘極漂浮stress所得到的衰退特性,可觀察到複晶矽薄膜電晶體一種新的高電場電流傳輸機制: 顆邊態輔助場射電流。另一方面,根據stress後再退火所得的特性及電流對stress時間的變化曲線顯示出:額外顆邊能態是一種半穩定能態,而介面態及氧化層陷入電荷則較不易被產生及消除。隨後我們探討製程條件及溫度對複晶矽薄膜電晶體之穩定度的影響。藉由利用閘極漂浮stress在複晶矽薄膜通道上產生顆邊態的結果顯示出,結晶步驟包含結核及顆粒成長兩個製程的複晶矽薄膜電晶體具有較佳的穩定度。再者,在複晶矽薄膜通道下的緩衝層若包含氮化矽層,則其將強化複晶矽薄膜電晶體的穩定度。此外,藉由變化stress過程的溫度,複晶矽薄膜電晶體的衰退程度顯示出與晶格聲子有密切相關。第九章摘要說明第二部分的結論。最後,第十章說明了本論文的主要貢獻並建議未來的研究方向。

In this thesis, the new analytical models and the characterization methods for the DC I-V characteristics of both the intrinsic a-Si TFT's and the intrinsic poly-Si TFT's have been established and verified experimentally. Furthermore, the reliability issues of the intrinsic poly-Si TFT's have been investigated and resolved based on their intrinsic transport mechanisms,on which the establishment of their I-V model is based. Due to the distinctly different physical mechanisms underlying the electrical characteristics between the intrinsic a-Si TFT's and the intrinsic poly-Si TFT's, the content of this thesis is mainly organized as two parts. First of all, a general introduction and the organization of this thesis are provided in Chapter 1. In PART ONE, we focus on the characterization and analysis of the intrinsic a-Si TFT's. Chapter 2 illustrates the previous works for the investigation of the a-Si TFT's and then, the fabrication process of test devices and organization of PART ONE are briefed. By considering the one-dimensional Poisson's equation based on an empirical model of the bulk trapped charges, Chapter 3 constructs the model of the surface charge density and the analytical C-V model for the intrinsic a-Si MIS capacitor. With the C-V model, the empirical parameters for trapped charges can be extracted from the experimental C-V curves. Based on the model of the surface charge density, Chapter 4 constructs the analytical I-V model of the intrinsic a-Si TFT's. Subsequently, an empirical model of the effective mobility is constructed with the densities of trapped and free electrons. From the effective mobility extracted, it is shown that only the empirical parameters of trapped charges extracted from the quasi-static C-V curves are appropriate for analyzing the DC I-V characteristics of the intrinsic a-Si TFT's. By including the effect of the parasitic resistance of source/drain junction into I-V model, the effective channel-length of the intrinsic a-Si TFT's can be extracted. To improve the deficiency for parameter extraction, a calibration loop is proposed. After the calibration procedure, the parasitic resistance extracted is independent of channel-length and only one set of parameters is needed for accurately simulating the transfer I-V characteristics of the intrinsic a-Si TFT's with various channel-lengths. Chapter 5 summarizes the conclusions of PART ONE. In PART TWO, we focus on the characterization and analysis of the intrinsic poly-Si TFT's and their reliability issues. Chapter 6 illustrates the previous works for the investigation of the poly-Si TFT's and the fabrication process of test devices and organization of PART TWO are then briefed. For analyzing the electrical characteristics of the intrinsic poly-Si TFT's, the grain-barrier height is an important physical quantity to be considered. The kink-behavior observed from the output curves in high VDS regime is another distinct feature of the intrinsic poly-Si TFT's. Chapter 7 begins with constructing the analytical model of the grain-barrier height by dividing the whole VGS regime into two parts. When VGS is smaller than VT0, based on the charge-neutrality condition and the fully-depleted condition of the whole grain, the grain-barrier height can be obtained as a function of the grain-size and the density of the grain-boundary(GB) states. When VGS is greater than VT0, due to the electrical coupling between the GB states and the gate-bias, the grain-barrier height is obtained by solving the Poisson's equation with quasi-two-dimensional method. Excellent agreements between the experimental and simulated results have been obtained by using the developed model with reasonable parameters. Subsequently, with the interfacial-layer thermionic-diffusion theory based on the model of the grain-barrier height established, the I-V model considering the DIGBL effect in low VDS regime is obtained. In high VDS regime, by assuming that the avalanche generation of electron-hole pairs is only initiated by the energetic electrons of DIGBL current, the new analytical I-V model is constructed. With reasonable parameters, good agreements are obtained between the experimental and simulated results over whole VDS regime for the intrinsic poly-Si TFTs of various channel-lengths. Subsequently, the temperature-dependence of IDS can be obtained analytically by invoking the developed I-V model. From the output curves measured with various temperature, IDS shows positive temperature-dependence in low VDS regime and negative in kink regime. The activation energy of IDS obtained from the Arrhenius plot also shows the same trend. These phenomena verify the temperature-dependence predicted by the new I-V model of the intrinsic poly-Si TFT's. Chapter 8 devotes to investigate the reliability issues of the intrinsic poly-Si TFT's. To resolve their degradation mechanisms, three intentioned stress schemes are performed to investigate the individual effects of the extra GB states, the interface states, and the oxide-trapped charges on the degraded characteristics. Based on the transport mechanisms discussed in the previous chapters, the degradation mechanisms are reasonably explained. Furthermore, from the degraded characteristics by floating-gate stress, a new high-field transport mechanism, the grain-boundary trap-assisted field emission current, is observed. On the other hand, the extra GB states generated by the floating-gate stress are shown to be metastable and the interface states and the oxide-trapped charges are shown to be harder to be created and annealed. Subsequently, the effects of the process conditions and temperature on the stability the reliability issues are investigated. By creating the extra GB states within the active poly-Si films with floating-gate stress, the intrinsic poly-Si TFT's with the crystallization condition composed of both processes of nucleation and grain-growth show better stability. In addition, the buffer layer, which is beneath the active poly-Si film, containing SiNx layer will also enhance device stability. With various temperature during stress, the degradation degree of the intrinsic poly-Si TFT's shows close relation to lattice phonons. The conclusions of PART TWO are summarized in Chapter 9. Finally, the major contributions of this thesis and the value works suggested for future investigation are summarized in Chapter 10.