基於最大可能性序列估計等化器應用於GSM系統之研究

Abstract

在GSM接收機中有三個重要的元件：RF/IF訊號處理器，等化器(Equalizer)以及通道解碼器(channel decoder)。這一篇論文主要研究的是GSM接收機所用的等化器(Equalizer)部分。 在發射機基頻調變的部分是採用一種簡化的GMSK調變器架構，此架構利用查表方式來產生GMSK的基頻調變訊號。在接收機的部分，由於調變訊號在經過通道時，會受到多重路徑的干擾，造成在接收端接收到的訊號會受到碼際干擾(Inter Symbol Interference)，產生解調上的困難，因此在接收機就需要利用等化器來消除碼際干擾。 GSM系統規定等化器必須能夠等化16ms的多重路徑延遲(multipath delay)； 一般使用於GSM系統的等化器可分為兩類：最大相似度序列估計(maximum likelihood sequence estimation)等化器及決策迴授等化器(decision feedback equalizer)。在這篇論文中主要研究的是兩種最大相似度序列估計等化器，分別是Forney與Ungerboeck提出的MLSE架構，並比較他們之間的異同。論文的最後，再把整個GSM傳輸系統在不同的靜態與動態的通道情形下做電腦模擬。

There are three key elements in a GSM receiver: RF/IF signal processing, the equalizer and the channel decoder. In this thesis, we focus on the study of equalizers used in the receiver. In the digital baseband Gaussian Minimum Shift Keying(GMSK) modulator, a new architecture of ROM table lookup is described. At the receiver, we need an equalizer to eliminate the inter-symbol interference(ISI) caused by the channel time dispersion due mainly to multipath propagation. The GSM specifications require a channel equalizer capable of handling multipath delay interval up to 16ms. Two different approaches are usually considered: an equalizer based on the maximum likelihood sequence estimation(MLSE) and a decision feedback equalizer(DFE). The purpose of this thesis is to compare two types of equalizers, both of which are based on the Viterbi Algorithm, proposed by Forney and Ungerboeck separately. Finally, computer simulation is used to characterize the performance of Ungerboeck's structure under a range of static and dynamic channel conditions.