標題: IEEE 802.11介 質 存 取 控 制 器 設 計 與 實 現:接 收 部 份
Design and Implementation of IEEE 802.11 MAC Controller:Receiver Part
作者: 洪銘聰
Ming-Tsung Hong
陳伯寧
Po-Ning Chen
電信工程研究所
關鍵字: 介質存取控制層處理器;無線區域網路;載波感測多重擷取及碰撞避免;IEEE 802.11;Medium Access Control Controller;Wireless Local Area Network;CSMA/CA
公開日期: 1998
摘要: 「網際網路」,一個蓬勃發展的嶄新領域。「無線通訊」,一個炙手可熱的明星產業。近年來拜可攜式電腦、數位通訊、低功率半導體元件技術的日益精進,網際網路正結合無線通訊的存取技術延伸出一個新的公眾網路型態-無線區域網路。1997年,IEEE 802.11 Specification 搶先在眾多無線區域網路標準中制訂完成,正式宣告了公眾無線區域網路的來臨。 二年來,雖然IEEE 802.11 相關無線網路產品不斷問世,但其中介質存取控制層處理器採用的設計方式多為Embedded System架構。CPU-based架構的最大優勢在於可適度修正韌體以達到『彈性化』的設計考量。隨著IEEE 802.11 Standard 的底定,唯一的彈性優勢也不再是必須的。 為因應成本的效益及高速傳輸的趨勢,論文中提出一套完整的介質存取控制系統方案。我們企圖以硬體方式實現IEEE 802.11介質存取控制層的機制,同時提供完整的對主機端與實體層的介面單元與直接記憶體存取控制器模組。最後,此結構將透過電腦輔助設計軟體來實現並將通過層層軟體及硬體的模擬與驗證。
「Internet」has become a new field with full vitality and 「Wireless Communication」 has grown rapidly as a profitable domain in the fashion. Recently, the advance in portable computers, digital communication, and low-power semiconductor technology makes feasible in incorporating Internet and wireless communication access technology and further leads to a new public network configuration- Wireless Local Area Network. In 1997, the standardization of IEEE 802.11 stole messes of wireless LAN specifications' thunder and thus formally declared the coming of the public wireless local network. In the past two years, the compliant wireless LAN products come on the scene successively. Most design approaches employ Embedded System architecture in MAC layer controllers. The feasibility of properly revising firmware in the architecture is their best advantage. However, the unique benefit is not necessary anymore after the emergence of the IEEE 802.11 standard. Under the considerations of cost and high transmission rate, a complete and viable solution for MAC system is presented in the thesis. We attempt to implement the mechanism over IEEE 802.11 MAC layer through hardwire approach and further provide the integrated interface modules for Host end and physical layer device as well as Direct Memory Access controller. The proposed architecture will be realized by CAD design tools, and then simulated and identified through scores of softwares and hardwares.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT870435045
http://hdl.handle.net/11536/64504
Appears in Collections:Thesis