語音編碼專用處理器

Abstract

語音傳輸是目前最主要也最普遍的通訊傳輸服務。在數位下語音的傳輸更有彈性，能夠降低價格、維持品質、並提供保密的功能。由於使用者的增加與有限的頻寬。新的語音編碼傳傳輸位元率已由8Kbps(CELP)與4.8Kbps(CS-ACELP)發展降至2.4Kbps(MELP、STC)。由於傳輸位元率的降低，語音的品質就只能由更複雜的演算法來提升，這使得即時實現語音編碼相當困難。 本論文提出一個新的語音編碼專用處理器。這個處理器專門設計處理線性預估與語調預估，這兩者均是語音編碼的核心技術。我們使用硬體-軟體雙重設計的方式使處理器的架構與指令集最佳化。並由於使用四級的管線式架構而得以平衡處理速度與晶片面積。它同時擁有兩個向量處理用的記憶體、24 bits精確的浮點運算單元、提供很大動態運算範圍的8 bits的指數處理單元以及具平行處理能力的指令。在指令長度固定為16 bits下，此處理器提供4種定址模式與三元運算。此晶片能於40MHz下工作，其處理能力約是TMS320C30的4.75倍。 此高性能的晶片使用TSMC 0.6um 1P3M CMOS製程，並以COMPASS Cell Library設計合成。晶片的面積約為23mm^2。此處理器並已被國科會晶片設計製作中心接受製作。

Speech communication is at present the most dominant and common service in telecommunication. Digital transmission of speech is more versatile, providing the opportunity of achieving costs, consistent quality, security and spectral efficiency in the systems that exploit it. Due to the increase in number of users and limited bandwidth available, the transmission bit rate of new digital speech coding techniques has dropped from 8 Kpbs (CELP), 4.8Kpbs (CS-ACELP) to 2.4 Kbps (MELP,STC). As the bit rate falling, the speech quality can only be maintained by employing very complex algorithms which are difficult to implement in real time. This thesis investigates a new application specific processor for speech coding processing. The processor is designed to process linear predictive coding and pitch estimation which are the kernels of speech coding techniques. We use hardware-software codesign methodology to optimize the processor architecture and instruction set. The processor use a four-stage pipeline to balance performance and core area. It has two memory banks for vector operation, 24-bit floating-point unit for precision, 8-bit exponent unit for large dynamic range operation and special instructions for parallel operation. Each instruction length is fixed as 16 bits. The instruction set provides 4 special addressing modes and 3-operand operations. This chip can run at 40MHz and the speed is about 4.75 times higher than that of TMS320C30. The chip is realized by using a TSMC 0.6mu 1P3M CMOS fabrication and synthesis by COMPASS cell library. The silicon area required for the core is approximately 23mm^2. This ASIC has been accepted by the National Science Council Chip Implementation Center (CIC) MPC project for fabrication in Taiwan R.O.C..