快閃記憶體式硬碟機控制器之完整系統設計與實現

Abstract

本篇論文主要是敘述一種資料儲存裝置的設計方法與實現，其主要目的是透過一控制器，將資料儲存在快閃記憶體內，並能有效的將錯誤的資料自行找出及更正。本論文的內容包含了硬碟機介面之設計原理、設計方法、以及快閃記憶體的管理方式。硬碟機介面採用了ATA-4之標準，傳輸速率可達到16.6MB/s。控制器內有一顆8051單晶片微控器，負責監督主機介面之訊號傳輸協定，並執行快閃記憶體之演算法，以有效的將快閃記憶體生命週期平均化，同時也增加系統之傳輸速率。內文中也敘述了各種測試方法與結果，以驗証本研究之達成率。

The theme of this thesis is mainly the description of the design and realization of a kind of data storage device. The main purpose of it is to store data in flash memory through a controller while errors can be located and corrected automatically. This report’s content covers the design theory and the methods of the interface in hard disk drives as well as the management of flash memory. The interface in hard disk drives adopt ATA-4 standard and the transfer rate of it can reach up to 16.6MB/Sec. In the controller there is a 8051 single-chip micro-processor which is responsible for monitoring host interfaces’ signal transfer agreement while execute the calculation of the flash memory, which is intentionally to evenly average the life cycle of the flash memory in an effective way and at the same time expedite the transfer rate of the system. And the content also describes all kinds of test methods and results in order to verify the achievement rate of this research.