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dc.contributor.authorHsieh, Yi-Binen_US
dc.contributor.authorKao, Yao-Huangen_US
dc.date.accessioned2014-12-08T15:08:29Z-
dc.date.available2014-12-08T15:08:29Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0786-6en_US
dc.identifier.urihttp://hdl.handle.net/11536/6545-
dc.description.abstractA new spread spectrum clock generator (SSCG) using double modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved and can optimize the jitter caused by the Sigma Delta modulator. In addition, the method of two-path is applied to reduce the capacitance value such that the total integration can be achieved. The proposed SSCG has been fabricated in a 0.18um CMOS process. The clock of 1.5GHz with down spread ratio of 0.5% is realized for applications to serial ATA. The 19.63dB EMI reduction (RBW=10KHz) and 35ps-pp period jitter are achieved in this study. The size of chip area is 0.44x0.48mm(2). The power consumption is 27mW.en_US
dc.language.isoen_USen_US
dc.titleA new spread spectrum clock generator for SATA using double modulation schemesen_US
dc.typeArticleen_US
dc.identifier.journalPROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCEen_US
dc.citation.spage297en_US
dc.citation.epage300en_US
dc.contributor.department傳播研究所zh_TW
dc.contributor.departmentInstitute of Communication Studiesen_US
dc.identifier.wosnumberWOS:000252233200068-
Appears in Collections:Conferences Paper