薄膜電晶體的尺寸效應與新結構之研究

Abstract

在本論文中，我們首先研究複晶矽薄膜電晶體的窄通道效應。由實驗結果發現，當複晶矽薄膜電晶體的寬度變小時，電晶體特性有明顯的改善，包括臨界電壓變小、次臨界波動(subthreshold swing)變小及電子遷移率(mobility)變大等。為了探討其原因，我們提出了一個具有物理意義的模型來模擬薄膜電晶體的輸出特性，該模型可適用在寬廣的閘極電壓、汲極電壓以及閘極寬度。由模擬結果得知當閘極寬度變小時，複晶矽通道內晶粒介面的深態缺陷密度(deep state density)與淺態缺陷密度(tail state density)皆隨之減小，所以元件特性獲得全面的改善。此外，我們也比較不同閘極長度和不同閘極寬度的次臨界波動，發現只要閘極的面積相同時，元件的次臨界波動亦相同，代表缺陷密度是因通道面積變小而變小。 我們也研究複晶矽薄膜電晶體的短通道效應。N型元件由於電子的碰撞游離係數(impact ionization rate)較大，所以其特性受到倍增崩潰(avalanche multiplication)與懸浮基板(floating-body)的影響，導致當閘極長度變小且汲極電壓變大時，臨界電壓與次臨界波動都變小，並有轉折效應(kink effect)產生。我們也發現當短通道效應與複晶矽的缺陷密度有深切關係，當缺陷密度因閘極寬度縮短而變小時，可抑制倍增崩潰效應並增加閘極電壓對通道的控制能力。經鈍化處理過的元件，其缺陷密度大量減小，幾乎沒有增崩潰效應，所以次臨界波動因穿透效應(punch-through effect)而變大。至於P型元件，由於電洞的碰撞游離係數較小，倍增崩潰較不明顯，所以當閘極長度縮短時，元件特性因為晶粒介面內的缺陷密度變小而獲得改善。 另外，為了降低複晶矽薄膜電晶體的漏電流，我們提出了一個新的方法來製作輕摻雜汲極薄膜電晶體。該方法利用液態沉積氧化矽(liquid phase deposition oxide)在複晶矽上會沉積，但在光阻上與氮化矽上不沉積的特性，選擇性的在複晶矽閘極側邊橫向沉積氧化矽間隙壁(oxide spacer)。此新結構具有製程成本低、製程簡單、製程溫度為室溫和氧化矽間隙壁是自我對準(self-aligned)等優點。實驗結果證實此新結構確實可有效降低汲極端空乏區的電場。使得漏電流變小，ON/OFF電流比有超過十倍的改善，轉折效應較不明顯，在元件可靠度方面也有顯著的改善。 底閘極非晶矽薄膜電晶體的特性深受非晶矽與氮化矽介面的影響，進而間接受到底閘極鋁金屬表面粗糙度的影響。本論文中我們結合化學機械研磨和高溫沉積鋁兩種技術來改善鋁閘極的表面粗糙度。和室溫沉積鋁相較，高溫沉積鋁熱穩定性佳，所以因熱製程所造成鋁閘極表面粗糙度的增加量大幅減少。但高溫沉積鋁的晶粒較大導致表面粗糙度大，這個缺點可由化學機械研磨克服。因此，以經化學機械研磨過的高溫沉積鋁所製作的底閘極非晶矽薄膜電晶體，其特性有顯著的改善。當鋁沉積溫度由室溫升高到400 OC時，臨界電壓由2.37 V降為1.43 V，遷移率0.32 cm2/V-s升高到1.36 cm2/V-s，次臨界波動由0.72 V/decade 降為 0.58 V/decade。

In this dissertation, we firstly investigate the narrow-width effects of polysilicon thin film transistors (poly-Si TFTs). With reducing channel width, TFT characteristics such as mobility, threshold voltage, and subthreshold swing are found to improve dramatically. To gain insight on the origin of the narrow-width effects, a physically-based analytical mode is proposed to simulate the output characteristics of poly-Si TFTs. Excellent fitting with the experimental data is observed over a wide range of drain bias, gate bias, and channel width. Our model shows that both the deep state density and tail state density are reduced with reducing channel width, thus accounting for the improved TFT characteristics with reducing channel width. In addition, subthreshold swings of poly-Si TFTs with various channel widths and lengths are compared. It is found the subthreshold swings of poly-Si TFTs with the same channel area are identical, indicating that the grain-boundary trap density is reduced due to the reduction of channel area. The short-channel effects of poly-Si TFTs are also investigated. For n-channel devices, because of the larger impact-ionization rate of electrons, their characteristics are affected by the avalanche multiplication as well as floating-body effect. As a result, both the threshold voltage and subthreshold swing are reduced and kink effect occurs when the channel length is small and drain bias is large. Since the short-channel effects are related to the grain-boundary trap density, the reduction of trap density due to scaling down the channel width can suppress the avalanche multiplication and enhance the gate bias control over the poly-Si channel. Furthermore, the trap density of passivated devices is reduced significantly, which in turn effectively suppress the avalanche multiplication. Consequently, the increased subthreshold swing due to punch-through effect rather than reduced subthreshold swing caused by avalanche multiplication is observed. As for p-channel devices, because of the small impact-ionization rate of holes, the avalanche-multiplication effect is not pronounced. Therefore, with scaling down the channel length and thus reducing trap density, the characteristics of p-channel devices are improved. We have also proposed a new lightly-doped-drain structure to reduce the anomalous leakage current of poly-Si TFTs. Since the liquid phase deposition (LPD) oxide can selectively deposit on the surface of poly-Si but not on the surfaces of photoresist and silicon nitride, the oxide spacer of this new device is formed by selective deposition of LPD oxide on the exposed sidewall of polycrystalline silicon gate. The process is simple, inexpensive, and can be performed at room temperature. Besides, the oxide spacer is self-aligned to the poly-Si gate. Our experimental results show that LPD oxide spacer of this new device is effective in reducing the electric field in the depletion region near the drain side. Compared to the device without oxide spacer, the leakage current of the new device is reduced dramatically and ON/OFF current ratio is improved by more than one order of magnitude. In addition, the kink effect is less pronounced and the reliability is improved in the new device. The characteristics of invert-staggered amorphous silicon (a-Si: H) TFT with a bottom gate is influenced by the interface at amorphous silicon and silicon nitride, and thus is influenced by the morphology of the Al bottom-gate metallurgy. We proposed a new method which combine the chemical mechanical polishing and high deposition temperature of Al gate to improve performance of inverted-staggered a-Si: H TFTs. We found that although the surface roughness of the as-deposited Al films increases with increasing deposition temperature, Al films deposited at higher temperature are more robust to hillock formation during subsequent annealing. To take advantage of the better hillock suppression properties, chemical mechanical polishing technique is employed to reduce the inherently large surface roughness of these high-temperature-deposited Al films. Our results show that the electrical characteristics of the TFTs are significantly improved. Specifically, the threshold voltage is reduced from 2.37 V to 1.43 V, the mobility is improved from 0.32 cm2/V-s to 1.36 cm2/V-s, and the subthreshold swing is improved from 0.72 V/decade to 0.58 V/decade as the Al deposition temperature is increased from 25 OC to 400 OC. 1-1 Overview of thin film transistor 1-2 Motivation 1-2-1 Dimensional effects on the characteristics of poly-Si TFTs 1-2-2 Leakage current of poly-Si TFTs 1-2-3 Interface effect between a-Si:H and a-SiNx:H of a-Si:H TFT 1-3 Thesis outline 1-4 Reference Chapter 2 Influences of Active Channel Geometry on Long Channel Polycrystalline Silicon Thin Film Transistors 2-1 Introduction 2-2 Experimenta 2-3 Results and discussions 2-3-1 Experimental results 2-3-2 A physically-based analytical model to extract deep state and tail state density 2-4 Summary 2-5 References Chapter 3 Influences of Active Channel Area and Plasma Treatment on Short Channel Polycrystalline Silicon Thin Film Transistors 3-1 Introduction 3-2 Experimenta 3-3 Results and discussions 4-3-1 Mechanisms of short-channel effects 4-3-2 Influences of active channel area and plasma treatment on short-channel effects 3-4 Summary 3-5 References Chapter 4 A Novel Lightly-Doped-Drain Polycrystalline Silicon Thin Film Transistors with Oxide Spacer Formed by One-Step Liquid Phase Deposition 4-1 Introduction 4-2 Experimental 4-3 Results and discussions 4-3-1 Growth Mechanism of LPD Oxide Deposition 4-3-2 Device Characteristics of Poly-Si TFTs with and without LPD Oxide Spacer 4-3-3 Hot-Carrier Reliability of Poly-Si TFTs with and without LPD Oxide Spacer 4-4 Summary 4-5 References Chapter 5 Improvements of Amorphous-Silicon Inverted-Staggered Thin-Film Transistors Using High-Temperature-Deposited Al Gate with Chemical Mechanical Polishing 5-1 Introduction 5-2 Experimental 5-3 Results and discussion 5-3 Summary 5-4 References Chapter 6 Conclusions and Recommendations for Future Study 6-1 Conclusions 6-2 Suggestions for future work