應用於硬體描述語言的一個有效率設計驗證輔助技術

Abstract

由於現在的電路設計的高複雜度，使得驗證已經成為設計流程中最主要的瓶頸，因此急需要一個實用的方法來降低驗證所需的時間。在製造測試中，有一個眾所皆知的技術可以用來減少測試時間，叫做“可測試性設計”(DFT)，它是在較難測試的地方加上一些額外的電路，使得可測性提高並減少測試時間。在這篇論文中，我們將類似的想法應用在功能驗證上，並提出一個有效的“設計驗證輔助” (DFV)技術來幫助使用者降低驗證時間。在一個硬體規格語言描述的設計中，我們清楚的定義了“較難控制”(HTC)程式碼的條件，並提出一個有效率的演算法來自動找到它們。除了找到這些較難控制的部分之外，我們也提出一個演算法，能夠以加入最少輔助程式碼的方式來消除這些部分。在加入這些輔助的程式碼後，我們便能很容易地以較少的輸入樣本達成高測試涵蓋率的目標，尤其對序列深度較深的設計特別有效。

Due to the high complexity of modern circuit designs, verification has become the major bottleneck of the entire design process. There is an emerging need for a practical solution to reduce the verification time. In the manufacturing test, a well-known technique used to reduce the testing time is the “design-for-testability” (DFT). By inserting some extra circuits on the hard-to-test points, the testability can be improved and the testing time can be decreased. In this thesis, we apply the similar idea to functional verification and propose an efficient “design-for-verification” (DFV) technique to help the users reduce the verification time. The conditions for hard-to-control (HTC) codes in a HDL design are clearly defined, and an efficient algorithm to detect them automatically is proposed. Besides the HTC detection, we also propose an algorithm that can eliminate those HTC points by inserting minimum number of assistant codes. After inserting those DFV codes, high test coverage can be easily obtained with less input patterns, especially for the deep-sequential designs. ABSTRACTION ii ACKNOWLEDGEMENTS iii CONTENTS iv LIST OF TABLES vi LIST OF FIGURES vii Chapter 1 Introduction……………………………………………1 Chapter 2 Previous Work…………………………………………7 2.1 Traditional Design for Testability Techniques…7 2.2 Design for Testability Techniques at RTL and Behavior Level………………………………………… 10 2.2.1 Modifying RTL Description to Enhance Testability …………………………………… 10 2.2.2 Non-Scan Approach………………………………10 2.2.3 Enhancing Control-Flow to Improve Testability………………………………………11 Chapter 3 HTC Detection…………………………………………13 3.1 Testability for Functional Verification…………13 3.2 The conditions of HTC Codes……………………… 14 3.3 The Extended S-Graph………………………………… 15 3.4 The Cost Function --- Sequential Depth………… 17 3.5 Sequential Depth Calculation……………………… 19 3.6 The Pseudo Codes……………………………………… 20 Chapter 4 HTC Elimination………………………………………24 4.1 Inserting DFV Code…………………………………… 24 4.2 Node Selection for Inserting DFV Code……………25 4.3 The Pseudo Codes……………………………………… 28 Chapter 5 Experimental Results……………………………… 29 Chapter 6 Conclusions……………………………………………32 References …………………………………………………………33