應用於系統晶片之共享記憶體介面單元分析與設計

Abstract

記憶體的使用，在超大型積體電路的系統設計中是不可或缺的，共享記憶體的硬體架構，更是常常被應用在許多超大型積體電路的設計上，尤其是許多系統單晶片上的應用。在這些應用中，記憶體的頻寬往往是影響整個系統效能的關鍵因素之一。一旦系統內，分享單一記憶體的功能單元增加，記憶體的頻寬，將成為整個系統效能提昇的瓶頸。為了要有效的使用共享記憶體系統中，有限的記憶體頻寬，過去已有許多研究專注在各種不同仲裁協定、或記憶體存取技術的設計，例如round-robin的仲裁方式、或管線化、時間共享的存取技術。藉由這些方法的改良，可以有效的縮短存取記憶體的時間，並增加整個系統的吞吐量。 在這篇論文中，我們提出了二階層式的仲裁方式，能夠有效的減少對共享記憶體的平均存取時間，同時提昇整個系統的吞吐量。由模擬的結果顯示，我們所提出二階層式的仲裁方式，和傳統rotating或round-robin的仲裁方式比較，對於共享記憶體的平均存取時間，節省了25%至30%。此外，為了加強在開發系統晶片的應用時，可重覆使用或客戶化設計的特性，我們設計了一個整合性的共享記憶體介面單元，此單元包括一個可程式的仲裁器，和一個記憶體控制器，透過網頁填寫系統所需的參數，即可自動產生。如此，可進一步縮短開發系統晶片所需的時間。

The shared-memory architecture is very popular in many VLSI system designs, especially in system-on-chip (SOC) applications. In those designs, the memory bandwidth is usually one of the most important factors dominating overall system performance. As the number of the sharing unit increases, the memory bandwidth could be a bottleneck. In order to improve the memory bandwidth in shared-memory systems, many research efforts have focused on reducing memory access time and increasing overall throughput by applying various kinds of arbitration protocols, or memory access techniques, such as round-robin, or pipelined, time-sharing techniques. In this thesis, we present a two-level arbitration scheme, which can significantly reduce the average access time (AAT) to the shared memory. Therefore, overall system throughput is enhanced due to fast memory access. Simulation results show that the AAT of the proposed two-level arbitration scheme can achieve 25% to 30% improvement compared with that of traditional rotating-priority, or round-robin, arbitration protocols. Besides, to enhance the reusability and customizability for SOC application developments, we proposed a shared-memory interface unit, which consists of a programmable arbiter, and a memory controller. Through the configuration of system requirements from web page, it can be auto-generated. As a result, the design cycle can be further reduced during the implementation of SOC designs. INTRODUCTION 1 1.1 MOTIVATION 1 1.2 SHARED-MEMORY SYSTEM FOR SOC APPLICATIONS 2 1.3 SOFT IP FOR SHARED-MEMORY INTERFACE UNIT 3 1.4 ORGANIZATION OF THIS THESIS 3 CHAPTER 2 5 DESIGN OF A 4-PORT CASCADABLE FAST ETHERNET SWITCHING HUB 5 2.1 INTRODUCTION TO ETHERNET 5 2.2 SWITCHING CONCEPTS 6 2.3 SWITCHING HUB OPERATIONS 7 2.3.1 Switching techniques 9 2.3.2 Switching methods 11 2.4 DESIGN OF A 4-PORT CASCADABLE SWITCHING HUB 13 2.4.1 System architecture 13 2.4.2 Cascading feature 15 2.4.3 MAC controller 16 2.4.4 Switch core 19 2.4.5 Memory management unit (MMU) 21 2.5 CHIP IMPLEMENTATION 26 2.5.1 System design flow 26 2.5.2 Implementation results 29 CHAPTER 3 32 ANALYSIS AND SIMULATION OF ARBITRATION SCHEMES 32 3.1 ARBITER IN SHARED-MEMORY INTERFACE UNIT 32 3.2 CLASSIFICATION OF ARBITRATION SCHEMES 33 3.2.1 Classified by architectures 33 3.2.2 Classified by protocols 34 3.3 DEFINITION OF SYSTEM REQUEST RATE 35 3.4 ROTATING-PRIORITY (ROUND-ROBIN) PROTOCOL 36 3.4.1 Equal request rate 36 3.4.2 Unequal request rate 36 3.5 FIXED-PRIORITY PROTOCOL 37 3.5.1 Equal request rate 37 3.5.2 Unequal request rate 37 3.6 TWO-LEVEL ARBITRATION SCHEME 37 3.6.1 Equal request rate 38 3.6.2 Unequal request rate 39 3.6.3 Grouping algorithm 40 3.7 SIMULATION RESULTS 41 CHAPTER 4 45 IP-BASED DESIGN FOR SHARED-MEMORY INTERFACE UNIT 45 4.1 INTRODUCTION TO SOC DESIGN 45 4.2 PROGRAMMABLE STAND-ALONE ARBITER 46 4.2.1 Functional description and architecture 46 4.1.2 Key features and claims 50 4.1.3 Configuration information and parameters 50 4.1.4 Specification of the programmable arbiter 52 4.3 MEMORY CONTROLLER 57 4.3.1 Synchronous SRAM controller 57 4.3.2 Synchronous DRAM controller 60 4.4 SHARED-MEMORY INTERFACE UNIT 66 4.4.1 Functional description 66 4.4.2 Utilization enhancement 69 4.5 WEB-BASED TECHNOLOGY 71 CHAPTER 5 74 CONCLUSION AND FUTURE WORK 74 5.1 CONCLUSION 74 5.2 FUTURE WORK 75 REFERENCES 77 APPENDIX I 79 PIN LIST OF 4-PORT CASCADABLE FAST ETHERNET SWITCH CONTROLLER 79