用於十六倍速數位多功能光碟讀取通道晶片之威特比解碼器

Abstract

在16倍數光碟系統上，碼際干擾(Inter-Symbol Interference)的情形就越嚴重，因此需要特殊的解碼技術加強解碼的能力，而部分響應最大近似(Partial Response Maximum Likelihood)即是其中之一。威特比解碼器(Viterbi Decoder)是其中的一個子電路，此電路的速度和效能將限制整個讀取通道晶片的效能。在此篇論文中，我們分析各種不同的參數對錯誤率(Error Rate)的影響，並決定使用何種參數值設計一個威特比解碼器，使解碼器的效能達到最佳，而這些參數包括多項式的次數、類比/數位轉換器的位元數等。在實現電路結構上，將限制執行速率的迴圈減短，原本在此迴圈中，加法-比較-選擇器為串接之形式，在此論文之中則將加法和比較同時平行處理，以達到我們所設定的十六倍數(418.56百萬取樣點/每秒)數位多功能光碟。

In a 16XS Digital Versatile Disc (DVD) system, the noise and Inter-Symbol Interference (ISI) are serious. Hence some special techniques are needed to solve the problem. The Partial Response Maximum Likelihood (PRML) is one of these techniques and Viterbi decoder is a subcircuit of this system. As we known, the operation frequency and performance of Viterbi decoder will limit the performance of the whole system. In the thesis, we have discussed in detail the relationship between the Error Rate and the various system parameters. After the detailed simulation, we can choose the appropriate values of these parameters to design a DVD detector, which has the best performance. These parameters include the polynomial order, the number of Analog-to-Digital Converter (ADC), etc. To obtain the high performance circuit, it is necessary to break the loop, since it limits the operation frequency of system. In this thesis, after some modifications, we utilize parallel structure instead of series structure and get the higher operation frequency. Abstract (English) ii Acknowledgements iii Table of Contents iv List of Tables vii List of Figures viii CHAPTER 1 INTRODUCTION 1 1.1 THE DVD SPECIFICATIONS 1 1.1.1. The history of DVD 1 1.1.2. Some problems of Communication System 2 1.2 THE DVD SYSTEM 2 1.2.1. The simple List of DVD Standard. 3 1.2.2. The precoding block of DVD system 4 1.2.3. The Channel of DVD system 4 1.2.4. The Detector of DVD system 5 1.3 THE READ CHANNEL IC OF DVD BASE ON PRML 6 CHAPTER 2 CHANNEL MODEL 8 2.1 PRINCIPLE OF PARTIAL RESPONSE 8 2.2 THE UNIDEAL OF CHANNEL 9 2.3 ASSUMPTION OF CHANNEL MODEL 11 CHAPTER 3 MAXIMUM LIKELIHOOD DECODER 13 3.1 MAXIMUM LIKELIHOOD (ML) 13 3.2 CONVOLUTIONAL CODE 15 3.2.1. Encoding of Convolutional Codes 15 3.2.2. State Diagrams of Convolutional Codes 16 3.2.3. Trellis of Convolutional Codes 17 3.3 VITERBI ALGORITHM 18 3.3.1. Viterbi Algorithm 18 3.3.2. The Path Memory and the Truncation Length 19 3.3.3. The method of decide the Output Data 20 3.3.4. M-step 21 3.4 THE VITERBI DECODER OF DVD 22 3.4.1. The Polynomial order. 22 3.4.2. The Branch metric and State metric 24 CHAPTER 4 SIMULATION AND ANALYSIS 26 4.1 THE ORDER OF POLYNOMIAL 29 4.2 THE MIDDLE VALUE OF VITERBI DECODER (ORDER =3) 37 4.3 THE BIT NUMBER OF ADC 40 4.4 THE METHODS OF CHOOSE OUTPUT AND THE LENGTH OF TRUNCATION LENGTH. 42 4.5 THE JITTER 54 4.6 M-STEP TRELLIS 56 4.7 THE METRICS. 57 CHAPTER 5 HARDWARE STRUCTURE 62 5.1 THE ACS CIRCUIT 63 5.2 THE BRANCH METRIC CIRCUIT 70 5.3 THE SURVIVAL PATH MEMORY AND SELECT OUTPUT DATA 71 CHAPTER 6 CONCLUSION AND FUTURE WORKS 74 References 76 Vita 80