功率放大器單石微波積體電路設計

Abstract

近年來隨著生活水準提升，無線通訊(wireless communication)市場快速成長，世界各國無不全力發展無線通訊高科技。在高頻前端模組中，功率放大器(power amplifier)主要置於發射機後級，其最大輸出功率(maximum output power)決定系統動態範圍(Dynamic Range, DR)的上限、功率增進效益(Power-Added Efficiency, PAE)則決定了系統使用之整體效率。 本篇論文之重點即在研究應用於高頻前端模組之關鍵零組件功率放大器之電路設計，論文中包含下列兩個主要部分：（1）功率放大器輸出反射損耗之改善；（2）功率放大器線性度之改善。 首先，由於傳統微波功率放大器在輸出端採用具有最大輸出功率之阻抗匹配時(power match)，存在高輸出反射損耗(output return loss)的缺點，本篇論文將針對此缺點提出不同於傳統的電路架構，使功率放大器本身在輸出端設計為具有最高輸出功率阻抗匹配的同時，亦能具有極佳的輸出端阻抗匹配，亦即低輸出反射損耗。如此一來在系統應用方面，可以避免掉isolator的使用，也可避免為了降低輸出反射損耗而使用功率分配、結合器或是distributed PA電路架構，因此，晶片面積將不會因此被犧牲掉。 另一方面，在無線通訊的應用上，功率放大器設計上的重要考量為功率增進效益及線性度(linearity)之間的取捨問題。功率增進效益影響到電池使用及待機時間的長短，而線性度則影響到訊號的輸出品質，以及數位通訊中不同頻道間，訊號彼此相互干擾程度，進而影響頻譜效率(spectral efficiency)。一般而言，我們必須將功率放大器操作在功率飽和區才能有較高的功率增進效益，然而在此同時卻大幅降低了功率放大器之線性度，因此，如何在功率增進效益與線性度之間作適當的取捨，是設計製作無線通訊相關應用之功率放大器的重要課題。利用傳統的線性化技術雖然可以同時兼顧兩者，不過發射機系統將會因此變得複雜，本篇論文中將由功率放大器本身著手，設計出同時具有高功率增進效益與高線性度的功率放大器，並以小信號模擬、大信號模擬、雙音模擬(two-tone simulation)、以及ACPR模擬，來監控功率放大器之電路特性。 本篇論文中所採用之製程係由漢威光電股份有限公司所提供之GaAs MESFET製程，而設計電路所需之各元件模型亦由該公司所提供，所使用的高頻電路模擬軟體為HP公司所研發的MDS。在完成電路模擬之後，我們並將實做一2400 MHz功率放大器之單石微波積體電路(Monolithic Microwave Integrated Circuit, MMIC)，以驗證模擬結果之準確性。實驗所得之功率放大器在一極寬的頻帶裡皆可維持有極低的輸出端反射損耗，其中輸出端VSWR之最低值可達1.04861；另一方面，數位調變之ACPR模擬，相較於傳統電路架構將可得到大於3 dBc的改善。經由模擬與實驗的結果，本論文所發展的功率放大器電路將可應用於一低價格、小體積之行動通訊裝備，在未來將針對其他射頻元件作整合而成唯一完整的射頻發射機模組。

In recent years, wireless communication has become the most important technology, and it has been developed rapidly in the world. In the high frequency front end, the power amplifier is the last stage of the transmitter module which signal will pass before transmitted. The dynamic range (DR) of the system depends on the maximum output power of the power amplifier, and the overall system efficiency depends on the power-added efficiency (PAE) of the power amplifier. The purpose of this thesis is to develop the circuit configuration of power amplifier for high frequency front-end module. There are two major parts in this research, including (1) the improvement of output return loss in power amplifiers, (2) the improvement of linearity in power amplifiers. At first, the conventional power amplifier circuit configuration exists an inherent drawback, i.e. when the output matching network is tuned for maximum output power, the output return loss is usually quite large. In this thesis, we will propose different power amplifier circuit configuration which has lower output return loss when the output matching network (OMN) is purely tuned for maximum output power. In this way, we can avoid using classical solutions for combination between power amplifier and other components in system applications, such as the use of isolators, the use of power divider/combiner, and the use of distributed power amplifier configuration. Therefore, the chip size will not be sacrificed any more. Secondly, for the application of wireless communication, the major parameter of power amplifier circuit design is the trade-off between power-added efficiency and linearity. The higher the power-added efficiency is, the longer lifetime the battery can be used. On the other hand, the higher the linearity is, the less the signal distortion is. Furthermore, the spectral efficiency will be higher due to the less inter-modulation between signals in adjacent channels. In general, to higher the power-added efficiency, the power amplifier should be operated at the output power saturation region. Unfortunately, it also lowers the linearity of the power amplifier. Consequently, a trade-off between efficiency and linearity should be carried out. Conventional linearization techniques can obtain both high efficiency and high linearity simultaneously, but the transmitter architecture will become complicated. In this thesis, we will improve the linearity based on the power amplifier circuit configuration itself not on the system approach. The simulation results such as small signal, large signal, IM3 of two-tone simulation, and ACPR will be used to monitor the power amplifier circuit performance. The used technology in this thesis is GaAs MESFET process proposed by HEXAWAVE inc., and all device models used in circuit simulations are also provided by the foundry. On the other hand, the simulation tool is the MDS provided by HP. After a systematic study of power amplifier circuit configurations, we also fabricated a 2400 MHz power amplifier MMIC test circuit to check the accuracy of the simulated results. The measured output VSWR of the microwave test circuit can keep a low value over a broad bandwidth, and the minimum output VSWR can be as low as 1.04861. On the other hand, the digital-modulated ACPR simulation also exhibited a 3dBc improvement over the power amplifier using classical configuration. It is believed that the proposed RF power amplifier circuit configuration can be applied to a low-cost small-size mobile equipment. Further research on the integration of other transmitter components will be conducted in the future. ABSTRACT (CHINESE) i ABSTRACT (ENGLISH) iii ACKNOWLEDGEMENT v CONTENTS vi TABLE CAPTIONS viii FIGURE CAPTIONS ix CHAPTER 1 INTRODUCTION 1.1 Background 1 1.2 Motivation 2 Fig. 1.1-1.2 4 CHAPTER 2 BASIC THEORY AND DESIGN METHODOLOGY 2.1 Scattering Parameters 6 2.2 Matches 7 2.3 Design Methodology of Power Amplifiers 9 2.3.1 DC Biasing Point 9 2.3.2 Stability 10 2.3.3 Single-Stage Power Amplifier Design Methodology 10 2.3.4 Two-Stage Power Amplifier Design Methodology 11 Fig. 2.1-2.4 13 CHAPTER 3 POWER AMPLIFIERS WITH LOW OUTPUT RETURN LOSS 3.1 Inherent Drawback of Conventional Power Amplifiers 15 3.2 Improvement of Output Return Loss 16 3.2.1 Single-Stage Power Amplifiers 17 3.2.2 Two-Stage Power Amplifiers 18 3.3 Results of Microwave Test Circuit 20 TABLE 3.1-3.2 22 Fig. 3.1-3.24 24 CHAPTER 4 LINEARITY ISSUE 47 4.1 Device Nonlinearities 47 4.2 Conventional Linearization Techniques 48 4.2.1 LINC 48 4.2.2 Feedforward 49 4.2.3 Feedback 50 4.2.4 Predistortion 50 4.3 Linearity Consideration 51 4.3.1 Linearity of CS Configuration 51 4.3.2 Linearity of CSPF Configuration 52 Fig. 4.1-4.9 54 CHAPTER 5 CONCLUSION AND FUTURE WORK 62 5.1 Main Results of This Thesis 62 5.2 Future Work 63 REFERENCES 64